Name: Xilinx ZCU106
Brand: Xilinx
Rating: 4 (1 reviews)

ZCU106 Board User Guide 145

UG1244 (v1.0) March 28, 2018 www.xilinx.com

Appendix B: Master Constraints File Listing

set_property IOSTANDARD LVCMOS12 [get_ports "SFP0_TX_DISABLE"] ;

#SFP1

set_property PACKAGE_PIN AF20 [get_ports "SFP1_TX_DISABLE"] ;

set_property IOSTANDARD LVCMOS12 [get_ports "SFP1_TX_DISABLE"] ;

set_property PACKAGE_PIN W1 [get_ports "SFP1_RX_N"] ;

set_property PACKAGE_PIN W2 [get_ports "SFP1_RX_P"] ;

set_property PACKAGE_PIN W5 [get_ports "SFP1_TX_N"] ;

set_property PACKAGE_PIN W6 [get_ports "SFP1_TX_P"] ;

set_property PACKAGE_PIN AF20 [get_ports "SFP1_TX_DISABLE"] ;

set_property IOSTANDARD LVCMOS12 [get_ports "SFP1_TX_DISABLE"] ;

#SFP COMMON

set_property PACKAGE_PIN W9 [get_ports "SFP_SI5328_OUT_C_N"] ;

set_property PACKAGE_PIN W10 [get_ports "SFP_SI5328_OUT_C_P"] ;

#SPF CLOCK RECOVERY

set_property PACKAGE_PIN G11 [get_ports "SFP_REC_CLOCK_C_N"] ;

set_property IOSTANDARD LVDS [get_ports "SFP_REC_CLOCK_C_N"] ;

set_property PACKAGE_PIN H11 [get_ports "SFP_REC_CLOCK_C_P"] ;

set_property IOSTANDARD LVDS [get_ports "SFP_REC_CLOCK_C_P"] ;

#I2C BUS

#I2C0

set_property PACKAGE_PIN AE19 [get_ports "PL_I2C0_SCL_LS"] ;

set_property IOSTANDARD LVCMOS12 [get_ports "PL_I2C0_SCL_LS"] ;

set_property PACKAGE_PIN AH23 [get_ports "PL_I2C0_SDA_LS"] ;

set_property IOSTANDARD LVCMOS12 [get_ports "PL_I2C0_SDA_LS"] ;

#I2C1

set_property PACKAGE_PIN AL21 [get_ports "PL_I2C1_SDA_LS"] ;

set_property IOSTANDARD LVCMOS12 [get_ports "PL_I2C1_SDA_LS"] ;

set_property PACKAGE_PIN AH19 [get_ports "PL_I2C1_SCL_LS"] ;

set_property IOSTANDARD LVCMOS12 [get_ports "PL_I2C1_SCL_LS"] ;

#SYSMON I2C

set_property PACKAGE_PIN B20 [get_ports "SYSMON_SDA_LS"] ;

set_property IOSTANDARD LVCMOS18 [get_ports "SYSMON_SDA_LS"] ;

set_property PACKAGE_PIN A22 [get_ports "SYSMON_SCL_LS"] ;

set_property IOSTANDARD LVCMOS18 [get_ports "SYSMON_SCL_LS"] ;

#MIO DISPLAY PORT

#Other net PACKAGE_PIN A30 - MIO27_DP_AUX_OUT Bank 501 - PS_MIO27

#Other net PACKAGE_PIN A31 - MIO28_DP_HPD Bank 501 - PS_MIO28

#Other net PACKAGE_PIN A32 - MIO29_DP_OE Bank 501 - PS_MIO29

#Other net PACKAGE_PIN A33 - MIO30_DP_AUX_IN Bank 501 - PS_MIO30

#USER MGT I/O

set_property PACKAGE_PIN AB3 [get_ports "SMA_MGT_RX_C_N"] ;

set_property PACKAGE_PIN AB4 [get_ports "SMA_MGT_RX_C_P"] ;

set_property PACKAGE_PIN AA5 [get_ports "SMA_MGT_TX_N"] ;

set_property PACKAGE_PIN AA6 [get_ports "SMA_MGT_TX_P"] ;

#USER MGT CLOCK

set_property PACKAGE_PIN AA9 [get_ports "USER_SMA_MGT_CLOCK_C_N"] ;

set_property PACKAGE_PIN AA10 [get_ports "USER_SMA_MGT_CLOCK_C_P"] ;

set_property PACKAGE_PIN U9 [get_ports "USER_MGT_SI570_CLOCK1_C_N"] ;

set_property PACKAGE_PIN U10 [get_ports "USER_MGT_SI570_CLOCK1_C_P"] ;

set_property PACKAGE_PIN R9 [get_ports "USER_MGT_SI570_CLOCK2_C_N"] ;

set_property PACKAGE_PIN R10 [get_ports "USER_MGT_SI570_CLOCK2_C_P"] ;

Brand	Xilinx
Model	ZCU106
Category	Motherboard
Language	English

Xilinx ZCU106 User Manual

Table of Contents

Other manuals for Xilinx ZCU106

Questions and Answers:

Xilinx ZCU106 Specifications

Related product manuals