Name: Xilinx ZCU106
Brand: Xilinx
Rating: 4 (1 reviews)

ZCU106 Board User Guide 146

UG1244 (v1.0) March 28, 2018 www.xilinx.com

Appendix B: Master Constraints File Listing

#UART

set_property PACKAGE_PIN AH17 [get_ports "UART2_TXD_O_FPGA_RXD"] ;

set_property IOSTANDARD LVCMOS12 [get_ports "UART2_TXD_O_FPGA_RXD"] ;

set_property PACKAGE_PIN AM15 [get_ports "UART2_RTS_O_B"] ;

set_property IOSTANDARD LVCMOS12 [get_ports "UART2_RTS_O_B"] ;

set_property PACKAGE_PIN AL17 [get_ports "UART2_RXD_I_FPGA_TXD"] ;

set_property IOSTANDARD LVCMOS12 [get_ports "UART2_RXD_I_FPGA_TXD"] ;

set_property PACKAGE_PIN AP17 [get_ports "UART2_CTS_I_B"] ;

set_property IOSTANDARD LVCMOS12 [get_ports "UART2_CTS_I_B"] ;

#SDI VIDEO

set_property PACKAGE_PIN B21 [get_ports "SDI_SCLK_LS"] ;

set_property IOSTANDARD LVCMOS18 [get_ports "SDI_SCLK_LS"] ;

set_property PACKAGE_PIN H23 [get_ports "SDI_MISO_LS"] ;

set_property IOSTANDARD LVCMOS18 [get_ports "SDI_MISO_LS"] ;

set_property PACKAGE_PIN L21 [get_ports "SDI_MOSI_LS"] ;

set_property IOSTANDARD LVCMOS18 [get_ports "SDI_MOSI_LS"] ;

set_property PACKAGE_PIN A9 [get_ports "SDI_CS_RCLKR_LS"] ;

set_property IOSTANDARD LVCMOS18 [get_ports "SDI_CS_RCLKR_LS"] ;

set_property PACKAGE_PIN J20 [get_ports "SDI_CS_RCVR_LS"] ;

set_property IOSTANDARD LVCMOS18 [get_ports "SDI_CS_RCVR_LS"] ;

set_property PACKAGE_PIN J19 [get_ports "SDI_CS_DRVR_LS"] ;

set_property IOSTANDARD LVCMOS18 [get_ports "SDI_CS_DRVR_LS"] ;

set_property PACKAGE_PIN E13 [get_ports "SDI_XALARM_RX_LS"] ;

set_property IOSTANDARD LVCMOS18 [get_ports "SDI_XALARM_RX_LS"] ;

set_property PACKAGE_PIN C14 [get_ports "SDI_XALARM_TX_LS"] ;

set_property IOSTANDARD LVCMOS18 [get_ports "SDI_XALARM_TX_LS"] ;

set_property PACKAGE_PIN AC1 [get_ports "SDI_MGT_RX_N"] ;

set_property PACKAGE_PIN AC2 [get_ports "SDI_MGT_RX_P"] ;

set_property PACKAGE_PIN AC5 [get_ports "SDI_MGT_TX_N"] ;

set_property PACKAGE_PIN AC6 [get_ports "SDI_MGT_TX_P"] ;

#AES3 AUDIO

set_property PACKAGE_PIN G7 [get_ports "AES_IN"] ;

set_property IOSTANDARD LVCMOS33 [get_ports "AES_IN"] ;

set_property PACKAGE_PIN AF13 [get_ports "AES_OUT_N"] ;

set_property IOSTANDARD DIFF_SSTL12 [get_ports "AES_OUT_N"] ;

set_property PACKAGE_PIN AE13 [get_ports "AES_OUT_P"] ;

set_property IOSTANDARD DIFF_SSTL12 [get_ports "AES_OUT_P"] ;

#PCIE

set_property PACKAGE_PIN L8 [get_ports "PCIE_PERST_B"] ;

set_property IOSTANDARD LVCMOS33 [get_ports "PCIE_PERST_B"] ;

set_property PACKAGE_PIN L10 [get_ports "PCIE_WAKE_B"] ;

set_property IOSTANDARD LVCMOS33 [get_ports "PCIE_WAKE_B"] ;

#PS GTR BANK 505

#Other net PACKAGE_PIN U30 - GT0_DP_TX_N Bank 505 - PS_MGTRTXN0_505

#Other net PACKAGE_PIN R30 - GT1_DP_TX_N Bank 505 - PS_MGTRTXN1_505

#Other net PACKAGE_PIN U29 - GT0_DP_TX_P Bank 505 - PS_MGTRTXP0_505

#Other net PACKAGE_PIN R29 - GT1_DP_TX_P Bank 505 - PS_MGTRTXP1_505

#Other net PACKAGE_PIN R34 - GT2_USB0_RX_N Bank 505 - PS_MGTRRXN2_505

#Other net PACKAGE_PIN R33 - GT2_USB0_RX_P Bank 505 - PS_MGTRRXP2_505

#Other net PACKAGE_PIN P32 - GT2_USB0_TX_N Bank 505 - PS_MGTRTXN2_505

#Other net PACKAGE_PIN P31 - GT2_USB0_TX_P Bank 505 - PS_MGTRTXP2_505

#Other net PACKAGE_PIN N34 - GT3_SATA1_RX_N Bank 505 - PS_MGTRRXN3_505

#Other net PACKAGE_PIN N33 - GT3_SATA1_RX_P Bank 505 - PS_MGTRRXP3_505

#Other net PACKAGE_PIN N30 - GT3_SATA1_TX_N Bank 505 - PS_MGTRTXN3_505

Brand	Xilinx
Model	ZCU106
Category	Motherboard
Language	English

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