Xilinx ZCU106 User Manual

ZCU106 Board User Guide 29
UG1244 (v1.0) March 28, 2018 www.xilinx.com
Chapter 3: Board Component Descriptions
The ZCU106 supports full power-off suspend mode where only the system controller and
the PS-side DDR4 SODIMM memory are powered. The DDR4 memory is kept in a
self-refresh state and has its reset input controlled by the system controller such that the
memory is not reset when waking-up from suspend mode. DDR4 SODIMM socket J1
connections are listed in Table 3-3.
Table 3-3: DDR4 SODIMM Socket J1 Connections to FPGA PS DDR Bank 504
XCZU7EV (U1) Pin Net Name
DDR4 SODIMM Memory J1
Pin Number Pin Name
AN34 DDR4_SODIMM_A0 144 A0
AM34 DDR4_SODIMM_A1 133 A1
AM33 DDR4_SODIMM_A2 132 A2
AL34 DDR4_SODIMM_A3 131 A3
AL33 DDR4_SODIMM_A4 128 A4
AK33 DDR4_SODIMM_A5 126 A5
AK30 DDR4_SODIMM_A6 127 A6
AJ30 DDR4_SODIMM_A7 122 A7
AJ31 DDR4_SODIMM_A8 125 A8
AH31 DDR4_SODIMM_A9 121 A9
AG31 DDR4_SODIMM_A10 146 A10/AP
AF31 DDR4_SODIMM_A11 120 A11
AG30 DDR4_SODIMM_A12 119 A12
AF30 DDR4_SODIMM_A13 158 A13
AE27 DDR4_SODIMM_BA0 150 BA0
AE28 DDR4_SODIMM_BA1 145 BA1
AD27 DDR4_SODIMM_BG0 115 BG0
AF27 DDR4_SODIMM_BG1 113 BG1
AP27 DDR4_SODIMM_DQ0 8 DQ0
AP25 DDR4_SODIMM_DQ1 7 DQ1
AP26 DDR4_SODIMM_DQ2 20 DQ2
AM26 DDR4_SODIMM_DQ3 21 DQ3
AP24 DDR4_SODIMM_DQ4 4 DQ4
AL25 DDR4_SODIMM_DQ5 3 DQ5
AM25 DDR4_SODIMM_DQ6 16 DQ6
AM24 DDR4_SODIMM_DQ7 17 DQ7
AM28 DDR4_SODIMM_DQ8 28 DQ8
AN28 DDR4_SODIMM_DQ9 29 DQ9
AP29 DDR4_SODIMM_DQ10 41 DQ10
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Xilinx ZCU106 Specifications

General

Brand	Xilinx
Model	ZCU106
Category	Motherboard
Language	English