Sequoia Series 123
STATus:QUEStionable:ENABle
This command sets or reads the value of the Questionable Enable register. This register is a mask for
enabling specific bits from the Questionable Event register to set the questionable summary (QUES)
bit of the Status Byte register. This bit (bit 3) is the logical OR of all the Questionable Event register
bits that are enabled by the Questionable Status Enable register.
Command Syntax STATus:QUESionable:ENABle <NRf+>
Parameters 0 to 32727
Default Value 0
Examples STAT:QUES:ENAB 18
Query Syntax STATus:QUEStionable:ENABle?
Returned Parameters <NR1>(Register value)
Related Commands STAT:QUES:EVEN?
STATus:QUEStionable:INSTrument:ISUMmary?
Phase Selectable
This command returns the value of the Questionable Event register for a specific output of a three-
phase power source. The particular output phase must first be selected by INST:NSEL.
The Event register is a read-only register, which holds (latches) all events that are passed by the
Questionable NTR and/or PTR filter. Reading the Questionable Event register clears it.
Query Syntax STATus:QUESionable:INSTrument:ISUMmary[:EVENt]?
Parameters None
Returned Parameters <NR1> (Register Value)
Examples STAT:QUES:INST:ISUM:EVEN?
Related Commands *CLS STAT:QUES:INST:ISUM:NTR STAT:QUES:INST:ISUM:PTR
STATus:QUEStionable:INSTrument:ISUMmary:CONDition?
Phase Selectable
This query returns the value of the Questionable Condition register for a specific output of a three-
phase power source. The particular output phase must first be selected by INST:NSEL. The Condition
register is a read-only register, which holds the real-time (unlatched) questionable status of the power
source.
Query Syntax STATus:QUEStionable:INSTrument:ISUMmary:CONDition?
Example STAT:QUES:INST:ISUM:COND?
Returned Parameters <NR1> (Register value)
STATus:QUEStionable:INSTrument:ISUMmary:ENABle
Phase Selectable
This command sets or reads the value of the Questionable Enable register for a specific output of a
three-phase power source. The particular output phase must first be selected by INST:NSEL. The
Enable register is a mask for enabling specific bits from the Questionable Event register to set the
questionable summary (QUES) bit of the Status Byte register. This bit (bit 3) is the logical OR of all the
Questionable Event register bits that are enabled by the Questionable Status Enable register.
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