Analog Devices AD9361

UG-570 AD9361 Reference Manual
| Page 102 of 128
Fig
ure 72. Transmitter Data Path, Dual Port TDD
FB_CLK
TX_FRAME
P0_D[11:0]
P1_D[11:0]
1R1T, DDR, TDD, DUAL PORT, 0x010 = 0xC8, 0x011 = 0x00, 0x012 = 0x08
T1_I[11:0] T1_I[11:0] T1_I[11:0] T1_I[11:0] T1_I[11:0] T1_I[11:0]
T1_Q[11:0] T1_Q[11:0] T1_Q[11:0] T1_Q[11:0] T1_Q[11:0] T1_Q[11:0]
11668-272
FB_CLK
TX_FRAME
P0_D[11:0]
P1_D[11:0]
2R2T, DDR, TDD, DUAL PORT, 0x010 = 0xC8, 0x011 = 0x00, 0x012 = 0x08
T1_I[11:0] T2_I[11:0] T1_I[11:0] T2_I[11:0] T1_I[11:0] T2_I[11:0]
T1_Q[11:0] T2_Q[11:0] T1_Q[11:0] T2_Q[11:0] T1_Q[11:0] T2_Q[11:0]
0
0
0
0
Rev. A