Analog Devices AD9361

Analog Devices AD9361

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UG-570 AD9361 Reference Manual

| Page 98 of 128

Fig

ure 67. Single Port Full Duplex Mode

DATA_CLK

RX_FRAME

P0_D[11:6]

FB_CLK

TXNRX

ENABLE

RX

DATA

RX

DATA

TX

DATA

TX

DATA

CTRL CTRL

PLL

FEEDBACK

CLK GEN

AD9361

BBP

TX_FRAME

P0_D[5:0]

11668-068

Rev. A

Table of Contents

General Information1
Table of Contents2
Revision History4
Introduction5
- Terminology5
- Register and Bit Syntax5
Initialization and Calibration6
- Overview6
- Initalization Calibrations7
- BBPLL VCO Calibration8
- RF Synthesizer Charge Pump Calibration8
- RF Synthesizer VCO Calibration8
- Baseband Rx Analog Filter Calibration9
- Baseband Tx Analog Filter Calibration10
- Baseband Tx Secondary Filter11
- Rx TIA Calibration Equations11
- Rx ADC Setup11
- Baseband DC Offset Calibration11
- Baseband DC Offset Tracking11
- RF DC Offset Calibration12
- Rx Quadrature Tracking Calibration13
- Tx Quadrature Calibration13
Reference Clock Requirements14
- Overview14
- DCXO Setup and Operation14
- Reference Clock Setup and Operation15
- Phase Noise Specification15
RF and BBPLL Synthesizer16
- Overview16
- RFPLL Introduction16
- AD9361 PLL Architecture16
- Reference Block16
- Main PLL Block17
- Charge Pump Current18
- RFPLL Loop Filter18
- VCO Configuration18
- VCO Calibration18
- VCO Vtune Measurement18
- Lock Detector18
- Synthesizer Look up Table19
- TDD Mode Faster Lock Times19
- External lo19
- Baseband PLL (BBPLL)19
- Bbpll Vco20
- BBPLL Charge Pump21
- BBPLL Loop Filter21
Fast Lock Profiles22
- Overview22
- Fast Lock Initial Wider BW Option22
- Configuring and Using a Fast Lock Profile23
- Fast Lock Pin Select24
Enable State Machine Guide25
- Overview25
- ENSM State Definitions25
- Modes of Operation26
- Sleep State30
Filter Guide31
- Overview31
- Tx Signal Path31
- Tx Digital Filter Blocks31
- Tx Analog Filter Blocks32
- Rx Signal Path33
- Rx Analog Filter Blocks33
- Rx Digital Filter Blocks33
- Digital Rx Block Delay34
Gain Control35
- Overview35
- Gain Control Threshold Detectors36
- LMT Overload Detector36
- ADC Overload Detector36
- Low Power Threshold36
- Average Signal Power36
- Settling Times37
- Peak Overload Wait Time37
- Settling Delay37
- Gain Table Overview37
- Full Table Mode37
- Split Table Mode38
- Digital Gain38
- MGC Overview38
- Slow Attack AGC Mode40
- Slow Attack AGC Gain Update Time40
- Overloads in Slow Attack AGC Mode41
- Slow Attack AGC and Gain Tables41
- Hybrid AGC Mode42
- Fast Attack AGC Mode42
- State 0: RESET43
- State 1: Peak Overload Detect43
- State 2: Measure Power and Lock Level Gain Change44
- State 3: Measure Power and Peak Overload Detect44
- State 4: Unlock Gain44
- State 5: Gain Lock and Measure Power45
Custom Gain Tables47
- Overview47
- RF DC Cal Bit49
- Maximum Full Table/Lmt Table Index49
- External LNA49
Received Signal Strength Indicator (RSSI)50
- Overview50
- Mode Select and Measurement Duration50
- RSSI Weighting50
- RSSI Delay and RSSI Wait50
- RSSI Preamble and RSSI Symbol51
- Rssi Rfir51
- RSSI Gain Step Calibration51
Transmit Power Control55
- Overview55
- Tx Attenuation Words55
- Attenuation Word Update Options55
Tx Power Monitor56
- Overview56
- Tx Power Monitor Description56
- Input Matching/Attenuation Network57
- Tx Power Monitor Gain Control58
- TPM Dynamic Range59
- EXAMPLE of Txmon CONFIGURATION and MEASUREMENT of TPM TRANSFER FUNCTION59
- TPM Test Mode60
RF Port Interface61
- Overview61
- Rx Signal Path Interface62
- Tx Signal Path Interface69
Factory Calibrations71
- Overview71
- Internal DCXO71
- Tx RSSI (Tx Monitor)71
- Rx RSSI71
- Rx GM/LNA Gain Step Calibration72
- Carrier Frequency72
Control Output73
- Overview73
- Description of Control Output Signals74
- 0X035 = 0X00 (Calibration Busy and Done)74
- 0X035 = 0X01 (PLL Lock)75
- 0X035 = 0X02 (Calibration Busy)75
- 0X035 = 0X03 (Rx Gain Control)75
- 0X035 = 0X04 (Rx Gain Control)76
- 0X035 = 0X05 (Rx Gain Control)76
- 0X035 = 0X06 (Rx Gain Control)76
- 0X035 = 0X07 (Rx Gain Control)76
- 0X035 = 0X08 (Rx Gain Control)76
- 0X035 = 0X09 (Rxon, Txon, RSSI)77
- 0X035 = 0X0A (Digital Overflow)77
- 0X035 = 0X0B (Calibration and ENSM States)77
- 0X035 = 0X0C (Gain Control)77
- 0X035 = 0X0D (Tx Quadrature and RF DC Calibration Status)78
- 0X035 = 0X0E (Rx Quadrature and BB DC Calibration Status)78
- 0X035 = 0X0F (Gain Control)78
- 0X035 = 0X10 (Gain Control and RSSI)78
- 0X035 = 0X11 (Auxadc Digital Output)78
- 0X035 = 0X12 (Gain Control, Power Word Ready)78
- 0X035 = 0X13 (Gain Control, Power Word Ready)79
- 0X035 = 0X14 (Digital Overflow)79
- 0X035 = 0X15 (DC Offset Tracking)79
- 0X035 = 0X16 (Gain Control)79
- 0X035 = 0X17 (Gain Control)80
- 0X035 = 0X18 (DC Offset Tracking, Power Word Ready)80
- 0X035 = 0X19 (Charge Pump Calibration States)80
- 0X035 = 0X1A (Rx VCO and ALC Calibration States)80
- 0X035 = 0X1B (Tx VCO and ALC Calibration States)80
- 0X035 = 0X1C (Rx VCO Calibration States)80
- 0X035 = 0X1D (Tx VCO Calibration States)80
- 0X035 = 0X1E (Gain Control, Temp Sense Valid, Auxadc Valid)81
- 0X035 = 0X1F (Gain Control)81
Auxadc/Auxdac/Gpo/Temp Sensor82
- Overview82
- Auxdac82
- Auxadc83
- Internal Temperature Sensor84
- General Purpose Output Control85
Baseband Synchronization87
- Overview87
- Multichip Synchronization87
- Procedure88
- Synchronization Verification89
Digital Interface Specification90
- Overview90
- CMOS Mode Data Path and Clock Signals91
- CMOS Maximum Clock Rates and Signal Bandwidths92
- Single Port Half Duplex Mode (CMOS)93
- Single Port TDD Functional Timing (CMOS)94
- Single Port Full Duplex Mode (CMOS)97
- Single Port FDD Functional Timing (CMOS)99
- Dual Port Half Duplex Mode (CMOS)100
- Dual Port TDD Functional Timing (CMOS)101
- Dual Port Full Duplex Mode (CMOS)103
- Dual Port FDD Functional Timing (CMOS)104
- Data Bus Idle and Turnaround Periods (CMOS)105
- Data Path Timing Parameters (CMOS)105
- LVDS Mode Data Path and Clock Signals106
- LVDS Mode Data Path Signals107
- REVISION HISTORY 6/15-Rev. 0 to Rev. a Change to Table 50108
- LVDS Maximum Clock Rates and Signal Bandwidths108
- Dual Port Full Duplex Mode (LVDS)109
- Data Path Functional Timing (LVDS)109
- Data Path Timing Parameters (LVDS)111
- Serial Peripheral Interface (SPI)113
- Additional Interface Signals116
Power Supply and Layout Guide117
- Overview117
- PCB Material and Stack up Selection117
- RF Transmission Line Layout118
- Fan-Out and Trace Space Guidelines119
- Component Placement and Routing Guidelines120
- Power Management and System Noise Considerations120
- Power Distributions for Different Power Supply Domains124
- Rx lo Frequency Deviations Due to Power Supply Transients126
Related Links128

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