Anritsu MP8931A - Page 146

Appendix A Specifications
A-4
(3) DVB-SPI interface
Item Specifications
Common
(I/O)
Connector
D_Sub 25 (Female)
Table Pin Contact Assignment
Pin
Signal
Pin
Signal
1 Clock A
14
Clock B
2 System GND
15
System GND
3
Data 7 A (MSB)
16
Data 7 B (MSB)
4 Data 6 A
17
Data 6 B
5 Data 5 A
18
Data 5 B
6 Data 4 A
19
Data 4 B
7 Data 3 A
20
Data 3 B
8 Data 2 A
21
Data 2 B
9 Data 1 A
22
Data 1 B
10
Data 0 A
23
Data 0 B
11
DVALID A
24
DVALID B
12
PSYNC A
25
PSYNC B
13
Cable shield
Logical conversion
1: Voltage of A is higher than that of B.
0: Voltage of A is lower than that of B.
Termination
100
Ω
Signal type
Data [7:0], Clock, Dvalid, Psync
Packet type
[1] 204: (1)+187+ (16) packets
[2] 188: (1)+187 packets
[3] 204: (1+3)+184+ (16) packets
[4] 188: (1+3)+184 packets
[5] 204: (1)+203 packets
[6] 204: (1+3)+200 packets
Output sig-
nal
Common to
Clock, Data
DVALID,
PSYNC
Level (LVDS)
Offset Voltage: 1.125 to 1.35 V
Differential Output Voltage: 247 to 454 mV
Tr/Tf (20 to 80%)
≤
T/7
Enable/Disable
Enable/disable (fixed to Low) setting
Data
Data out of PN
range
“Sync”: 47 h (fixed)
“16 Valid extra bytes”, “PID”: ALL1 (fixed)
DVALID
Level
Fixed to “High”
Clock
(byte clock)
Frequency
10 kHz to 13.5 MHz, Resolution: 1 Hz
Duty
50%
±
10%
Phase
t
Data/PSYNC
Clock
T
| t |
≤
T/10
T=1/f