Anritsu MP8931A - Page 147

Appendix A Specifications
A-5
Item Specifications
Input signal
Common to
Clock, Data
DVALID,
PSYNC
Level (LVDS)
0.1 to 2.0 Vp-p
Data
Data out of PN
range
Data are not compared for “Sync,” “16 Valid extra
bytes” or “PID.”
Clock
(byte clock)
Frequency
10 kHz to 13.5 MHz
Duty
50%
±
10%
Phase
td
Data/PSYNC/
DVALID
Clock
T
Clock Period: T = 1/f
Data Hold Time: td = T/2
±
T/10
Monitor output
Enable/disable (high-impedance) setting
Note:
An external clock (byte clock) can be used when this interface is
selected. Refer to Section 4.2.7 “External clock setting” for details
including settings.