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Anritsu MT1040A - Page 614

Anritsu MT1040A
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PCS Skew InsertionPCS Skew Insertion
WAN OH CaptureWAN OH Capture
Frame CaptureFrame Capture
TransceiverTransceiver
LOA (Loss of alignment) (For 400 Gbps)
High SER (For 400 Gbps)
Bits:
0 to 4224 (For 100 Gbps Tx lane),
0 to 8448 (For 40 Gbps, 100 Gbps Physical lane)
0 to 8000 (For 400 Gbps Tx lane)
Item
SOH/TOH: 64 Frames
POH: 64 Frames
Pathtrace:J0/J1/J2 (Displays in ASCII characters)
Timing
Single
Repeat : Update period 1s
Buffer size
1024 KB
Frame slicing
Whole frame, Top 64 Bytes, Top 128 Bytes
Buffer handling
Stop when full, Overwrite
Capture transmitted frames
on, off
Trigger Type
Manual, Error, Field match
Trigger Position
Top, Middle (Only when Trigger Type is Error/Field match)
Error Type
Any Type, Fragment, Oversize or undersize, Oversize, Undersize, FCS error
Module Present
Transceiver Information
Alarm, Wavelength and bit rate, Compliance, Vendor Information, Output
Control
Power monitor
MDIO analysis
For QSFP56, QSFP-DD, OSFP:
NVR1, NVR2, Module FAWS, MW Lane FAWS, CTRL, MDIO Read/Write
I2C analysis
For QSFP+ and QSFP28:
Lower, Lower (Lane), Upper (00), Upper (03), Read/Write
For SFP, SFP+, and SFP28:
Memory A0h, Memory A2h, Read/Write
Setting
VOD, Pre, Post, DFE
SpecificationsSpecifications
614614

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