ARM Cortex-A9 MBIST User Manual

List of Figures
x Copyright © 2008 ARM Limited. All rights reserved. ARM DDI 0414C
Non-Confidential
Restricted Access
Figure 2-17 Detecting an MBIST failure ..................................................................................... 2-16
Figure 2-18 Start of data log retrieval ......................................................................................... 2-17
Figure 2-19 End of data log retrieval .......................................................................................... 2-17
Figure 2-20 Start of bitmap data log retrieval ............................................................................. 2-18
Figure 2-21 End of bitmap data log retrieval .............................................................................. 2-19
Figure 3-1 MBIST instruction register control unit ...................................................................... 3-2
Figure 3-2 MBIST instruction register dispatch unit ................................................................... 3-2
Figure 4-1 MBIST Datalog Register format ................................................................................ 4-2

ARM Cortex-A9 MBIST Specifications

General

Architecture	ARMv7-A
Clock Speed	Up to 2 GHz
Memory Management Unit	Yes
TrustZone	Yes
Core Count	1-4
Instruction Set	ARM, Thumb-2
Pipeline	8-stage
Floating Point Unit	VFPv3
NEON	Optional
L1 Cache	32KB Instruction, 32KB Data, per core
MBIST	Built-in Memory BIST