ARM Cortex-A9 MBIST User Manual

ARM DDI 0414C Copyright © 2008 ARM Limited. All rights reserved. ix
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List of Figures
Cortex-A9 MBIST Controller Technical
Reference Manual
Key to timing diagram conventions ............................................................................ xiv
Figure 1-1 Cortex-A9 MBIST configuration ................................................................................ 1-2
Figure 1-2 MBIST controller wiring diagram ............................................................................... 1-3
Figure 1-3 Traditional method of interfacing MBIST ................................................................... 1-4
Figure 1-4 Cortex-A9 processor MBIST interface ...................................................................... 1-5
Figure 2-1 Data In for Instruction data RAM and Data data RAM .............................................. 2-5
Figure 2-2 Data Out for Instruction data RAM and Data data RAM ........................................... 2-5
Figure 2-3 Data in for Instruction tag RAM ................................................................................. 2-6
Figure 2-4 Data out for Instruction tag RAM ............................................................................... 2-7
Figure 2-5 Data in for Data tag RAM and SCU tag RAM ........................................................... 2-7
Figure 2-6 Data out for Data tag RAM and SCU tag RAM ......................................................... 2-7
Figure 2-7 Data in for Outer RAM ............................................................................................... 2-8
Figure 2-8 Data out for Outer RAM ............................................................................................ 2-8
Figure 2-9 Data in for BTAC RAM .............................................................................................. 2-9
Figure 2-10 Data out for BTAC RAM ............................................................................................ 2-9
Figure 2-11 Data in for TLB RAM ................................................................................................. 2-9
Figure 2-12 Data out for TLB RAM ............................................................................................. 2-10
Figure 2-13 Data in for GHB RAM .............................................................................................. 2-10
Figure 2-14 MBIST controller block ............................................................................................ 2-11
Figure 2-15 Loading the MBIST controller instruction ................................................................ 2-15
Figure 2-16 Starting the MBIST test ........................................................................................... 2-16

ARM Cortex-A9 MBIST Specifications

General

Architecture	ARMv7-A
Clock Speed	Up to 2 GHz
Memory Management Unit	Yes
TrustZone	Yes
Core Count	1-4
Instruction Set	ARM, Thumb-2
Pipeline	8-stage
Floating Point Unit	VFPv3
NEON	Optional
L1 Cache	32KB Instruction, 32KB Data, per core
MBIST	Built-in Memory BIST