To Next Page

To Previous Page

List of Tables

Non-Confidential

Restricted Access

Table 3-11 CacheSize field encoding ....................................................................................... 3-13

Table A-1 MBIST controller interface signals ............................................................................ A-2

Table A-2 MBISTARRAY one-hot chip enables ........................................................................ A-2

Table A-3 Miscellaneous signals ............................................................................................... A-4

Table B-1 Differences between issue A and issue B ................................................................ B-1

Table B-2 Differences between issue B and issue C ................................................................ B-1

Questions and Answers:

Need help?

Do you have a question about the ARM Cortex-A9 MBIST and is the answer not in the manual?

ARM Cortex-A9 MBIST Specifications

General

Architecture	ARMv7-A
Clock Speed	Up to 2 GHz
Memory Management Unit	Yes
TrustZone	Yes
Core Count	1-4
Instruction Set	ARM, Thumb-2
Pipeline	8-stage
Floating Point Unit	VFPv3
NEON	Optional
L1 Cache	32KB Instruction, 32KB Data, per core
MBIST	Built-in Memory BIST