ARM Cortex-A9 MBIST User Manual

ARM DDI 0414C Copyright © 2008 ARM Limited. All rights reserved. vii
Restricted Access Non-Confidential
List of Tables
Cortex-A9 MBIST Controller Technical
Reference Manual
Change history .............................................................................................................. ii
Table 1-1 Cortex-A9 processor MBIST interface signals .......................................................... 1-6
Table 2-1 Cortex-A9 signal settings for MBIST ......................................................................... 2-2
Table 2-2 RAM arrays and MBIST controller interfaces ............................................................ 2-2
Table 2-3 Data data RAM byte write enable control .................................................................. 2-5
Table 2-4 MBISTARRAY bit usage for tag RAMs ..................................................................... 2-6
Table 2-5 Tag RAM control ....................................................................................................... 2-8
Table 2-6 MBISTTX signals .................................................................................................... 2-11
Table 2-7 MBISTRX signals .................................................................................................... 2-12
Table 2-8 MBIST controller top level I/O ................................................................................. 2-13
Table 2-9 Data log format ........................................................................................................ 2-18
Table 3-1 Pattern field encoding ............................................................................................... 3-4
Table 3-2 Go/No-Go test pattern ............................................................................................... 3-6
Table 3-3 Control field encoding (five LSB bits) ........................................................................ 3-7
Table 3-4 Read latency field encoding ...................................................................................... 3-8
Table 3-5 Write latency field encoding ...................................................................................... 3-8
Table 3-6 MBIR[39:36] CPU mapping ....................................................................................... 3-9
Table 3-7 MaxXAddr field encoding ........................................................................................ 3-10
Table 3-8 MaxYAddr field encoding ........................................................................................ 3-10
Table 3-9 ArrayEnables field encoding ................................................................................... 3-11
Table 3-10 ColumnWidth field encoding ................................................................................... 3-13

ARM Cortex-A9 MBIST Specifications

General

Architecture	ARMv7-A
Clock Speed	Up to 2 GHz
Memory Management Unit	Yes
TrustZone	Yes
Core Count	1-4
Instruction Set	ARM, Thumb-2
Pipeline	8-stage
Floating Point Unit	VFPv3
NEON	Optional
L1 Cache	32KB Instruction, 32KB Data, per core
MBIST	Built-in Memory BIST