33
2467S–AVR–07/09
ATmega128
External Memory
Control Register B –
XMCRB
• Bit 7– XMBK: External Memory Bus-keeper Enable
Writing XMBK to one enables the bus keeper on the AD7:0 lines. When the bus keeper is
enabled, it will ensure a defined logic level (zero or one) on AD7:0 when they would otherwise
be tri-stated. Writing XMBK to zero disables the bus keeper. XMBK is not qualified with SRE, so
even if the XMEM interface is disabled, the bus keepers are still activated as long as XMBK is
one.
• Bit 6..4 – Res: Reserved Bits
These are reserved bits and will always read as zero. When writing to this address location,
write these bits to zero for compatibility with future devices.
• Bit 2..0 – XMM2, XMM1, XMM0: External Memory High Mask
When the External Memory is enabled, all Port C pins are default used for the high address byte.
If the full 60KB address space is not required to access the External Memory, some, or all, Port
C pins can be released for normal Port Pin function as described in Table 5. As described in
“Using all 64KB Locations of External Memory” on page 35, it is possible to use the XMMn bits to
access all 64KB locations of the External Memory.
Using all Locations of
External Memory
Smaller than 64 KB
Since the external memory is mapped after the internal memory as shown in Figure 11, the
external memory is not addressed when addressing the first 4,352 bytes of data space. It may
appear that the first 4,352 bytes of the external memory are inaccessible (external memory
addresses 0x0000 to 0x10FF). However, when connecting an external memory smaller than 64
KB, for example 32 KB, these locations are easily accessed simply by addressing from address
0x8000 to 0x90FF. Since the External Memory Address bit A15 is not connected to the external
memory, addresses 0x8000 to 0x90FF will appear as addresses 0x0000 to 0x10FF for the exter-
nal memory. Addressing above address 0x90FF is not recommended, since this will address an
external memory location that is already accessed by another (lower) address. To the Applica-
tion software, the external 32 KB memory will appear as one linear 32 KB address space from
0x1100 to 0x90FF. This is illustrated in Figure 17. Memory configuration B refers to the
ATmega103 compatibility mode, configuration A to the non-compatible mode.
When the device is set in ATmega103 compatibility mode, the internal address space is 4,096
bytes. This implies that the first 4,096 bytes of the external memory can be accessed at
Bit 76543210
XMBK – – – – XMM2 XMM1 XMM0 XMCRB
Read/Write R/W R R R R R/W R/W R/W
Initial Value00000000
Table 5. Port C Pins Released as Normal Port Pins when the External Memory is Enabled
XMM2 XMM1 XMM0 # Bits for External Memory Address Released Port Pins
0 0 0 8 (Full 60 KB space) None
0017 PC7
0106 PC7 - PC6
0115 PC7 - PC5
1004 PC7 - PC4
1013 PC7 - PC3
1102 PC7 - PC2
1 1 1 No Address high bits Full Port C
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