32
2467S–AVR–07/09
ATmega128
• Bit 6..4 – SRL2, SRL1, SRL0: Wait-state Sector Limit
It is possible to configure different wait-states for different External Memory addresses. The
external memory address space can be divided in two sectors that have separate wait-state bits.
The SRL2, SRL1, and SRL0 bits select the split of the sectors, see Table 3 and Figure 11. By
default, the SRL2, SRL1, and SRL0 bits are set to zero and the entire external memory address
space is treated as one sector. When the entire SRAM address space is configured as one sec-
tor, the wait-states are configured by the SRW11 and SRW10 bits.
• Bit 1 and Bit 6 MCUCR – SRW11, SRW10: Wait-state Select Bits for Upper Sector
The SRW11 and SRW10 bits control the number of wait-states for the upper sector of the exter-
nal memory address space, see Table 4.
• Bit 3..2 – SRW01, SRW00: Wait-state Select Bits for Lower Sector
The SRW01 and SRW00 bits control the number of wait-states for the lower sector of the exter-
nal memory address space, see Table 4.
Note: 1. n = 0 or 1 (lower/upper sector).
For further details of the timing and wait-states of the External Memory Interface, see Figures
13 through Figures 16 for how the setting of the SRW bits affects the timing.
• Bit 0 – Res: Reserved Bit
This is a reserved bit and will always read as zero. When writing to this address location, write
this bit to zero for compatibility with future devices.
Table 3. Sector limits with different settings of SRL2..0
SRL2 SRL1 SRL0 Sector Limits
0 0 0 Lower sector = N/A
Upper sector = 0x1100 - 0xFFFF
0 0 1 Lower sector = 0x1100 - 0x1FFF
Upper sector = 0x2000 - 0xFFFF
0 1 0 Lower sector = 0x1100 - 0x3FFF
Upper sector = 0x4000 - 0xFFFF
0 1 1 Lower sector = 0x1100 - 0x5FFF
Upper sector = 0x6000 - 0xFFFF
1 0 0 Lower sector = 0x1100 - 0x7FFF
Upper sector = 0x8000 - 0xFFFF
1 0 1 Lower sector = 0x1100 - 0x9FFF
Upper sector = 0xA000 - 0xFFFF
1 1 0 Lower sector = 0x1100 - 0xBFFF
Upper sector = 0xC000 - 0xFFFF
1 1 1 Lower sector = 0x1100 - 0xDFFF
Upper sector = 0xE000 - 0xFFFF
Table 4. Wait States
(1)
SRWn1 SRWn0 Wait States
0 0 No wait-states
0 1 Wait one cycle during read/write strobe
1 0 Wait two cycles during read/write strobe
1 1 Wait two cycles during read/write and wait one cycle before driving out
new address
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