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Atmel ATmega32M1 User Manual

Atmel ATmega32M1
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105
7647H–AVR–03/12
Atmel ATmega16/32/64/M1/C1
If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the
counter even if the pin is configured as an output. This feature allows software control of the
counting.
12.8.3 Timer/Counter Register – TCNT0
The Timer/Counter Register gives direct access, both for read and write operations, to the
Timer/Counter unit 8-bit counter. Writing to the TCNT0 Register blocks (removes) the Compare
Match on the following timer clock. Modifying the counter (TCNT0) while the counter is running,
introduces a risk of missing a Compare Match between TCNT0 and the OCR0x Registers.
12.8.4 Output Compare Register A – OCR0A
The Output Compare Register A contains an 8-bit value that is continuously compared with the
counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to
generate a waveform output on the OC0A pin.
12.8.5 Output Compare Register B – OCR0B
The Output Compare Register B contains an 8-bit value that is continuously compared with the
counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to
generate a waveform output on the OC0B pin.
12.8.6 Timer/Counter Interrupt Mask Register – TIMSK0
Bits 7..3 – Res: Reserved Bits
These bits are reserved bits in the ATmega16/32/64/M1/C1 and will always read as zero.
Bit 2 – OCIE0B: Timer/Counter Output Compare Match B Interrupt Enable
When the OCIE0B bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter Compare Match B interrupt is enabled. The corresponding interrupt is executed if
a Compare Match in Timer/Counter occurs, i.e., when the OCF0B bit is set in the Timer/Counter
Interrupt Flag Register – TIFR0.
Bit 76543210
TCNT0[7:0] TCNT0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
OCR0A[7:0] OCR0A
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
OCR0B[7:0] OCR0B
Read/Write R/WR/WR/WR/WR/WR/WR/WR/W
Initial Value00000000
Bit 76543210
OCIE0B OCIE0A TOIE0 TIMSK0
Read/Write R R R R R R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0

Table of Contents

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Atmel ATmega32M1 Specifications

General IconGeneral
Architecture8-bit AVR
Flash Memory32 KB
SRAM2 KB
EEPROM1 KB
Clock Speed16 MHz
GPIO Pins32
I/O Pins32
ADC Channels8
ADC Resolution10-bit
UART1
USART1
SPI1
I2C1
PWM Channels6
CAN1
Operating Voltage2.7V - 5.5V
Operating Temperature-40°C to +85°C
Temperature Range-40°C to +85°C
Package44-TQFP, 44-QFN

Summary

Features

AVR CPU Core

Reset and Interrupt Handling

Explanation of interrupt sources, vectors, priority levels, and behavior during interrupt execution.

System Clock

System Clock Prescaler

Details on the CLKPR register for dividing the system clock to reduce power consumption and affect peripheral frequencies.

Power Management and Sleep Modes

8-bit Timer/Counter0 with PWM

Modes of Operation

Detailed explanation of Normal, CTC, and various PWM modes for Timer/Counter0 operation.

Controller Area Network - CAN

CAN Protocol

Explanation of the CAN protocol principles, standards, and message transmission priorities.

Error Management

Description of error detection mechanisms (message and bit level) and fault confinement states.

Analog to Digital Converter - ADC

Features

List of ADC capabilities including resolution, accuracy, conversion time, input channels, and reference voltages.

Starting a Conversion

Procedures for initiating ADC conversions, including single conversion and auto-triggering modes.

debugWIRE On-chip Debug System

Features

Overview of debugWIRE capabilities including program flow control, real-time operation, and symbolic debugging.

Boot Loader Support – Read-While-Write Self-Programming ATmega16/32/64/M1/C1

Self-Programming the Flash

Procedures and considerations for programming the Flash memory using the SPM instruction.

Memory Programming

Electrical Characteristics

Absolute Maximum Ratings*

Critical voltage, current, and temperature limits that must not be exceeded for device reliability.

Instruction Set Summary

Register Summary

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