Atmel ATmega32M1 User Manual

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7647H–AVR–03/12
Atmel ATmega16/32/64/M1/C1
Figure 18-6. ADC Timing Diagram, Auto Triggered Conversion
Figure 18-7. ADC Timing Diagram, Free Running Conversion
18.5 Changing Channel or Reference Selection
The MUXn and REFS1:0 bits in the ADMUX Register are single buffered through a temporary
register to which the CPU has random access. This ensures that the channels and reference
selection only takes place at a safe point during the conversion. The channel and reference
selection is continuously updated until a conversion is started. Once the conversion starts, the
channel and reference selection is locked to ensure a sufficient sampling time for the ADC. Con-
tinuous updating resumes in the last eight ADC clock cycle before the conversion completes
(ADIF in ADCSRA is set). Note that the conversion starts on the second following rising CPU
clock edge after ADSC is written. The user is thus advised not to write new channel or reference
selection values to ADMUX until two ADC clock cycle after ADSC is written.
Table 18-1. ADC Conversion Time
Condition First Conversion
Normal
Conversion,
Single Ended
Auto Triggered
Conversion
Sample & Hold
(Cycles from Start of Conversion)
13.5 3.5 2
Conversion Time
(Cycles)
25 15.5 16
1 2 3 4 5 6 7 8 11 12 13 14
Sign and MSB of Result
LSB of Result
ADC Clock
Trigger
Source
ADIF
ADCH
ADCL
Cycle Number
12
One Conversion Next Conversion
Conversion
Complete
Prescaler
Reset
ADATE
Prescaler
Reset
Sample &
Hold
MUX and REFS
Update
12 13 14
Sign and MSB of Result
LSB of Result
ADC Clock
ADSC
ADIF
ADCH
ADCL
Cycle Number
12
One Conversion Next Conversion
34
Conversion
Complete
Sample & Hold
MUX and REFS
Update
5

Atmel ATmega32M1 Specifications

General

Brand	Atmel
Model	ATmega32M1
Category	Microcontrollers
Language	English