Atmel ATmega32M1

324
7647H–AVR–03/12
Atmel ATmega16/32/64/M1/C1
26.9 Parallel Programming Characteristics
Figure 26-5. Parallel Programming Timing, Including some General Timing Requirements
Figure 26-6. Parallel Programming Timing, Loading Sequence with Timing Requirements
(1)
Note: 1. The timing requirements shown in Figure 25-7 (i.e., t
DVXH
, t
XHXL
, and t
XLDX
) also apply to load-
ing operation.
Data & Contol
(DATA, XA0/1, BS1, BS2)
XTAL1
t
XHXL
t
WLWH
t
DVXH
t
XLDX
t
PLWL
t
WLRH
WR
RDY/BSY
PAGEL
t
PHPL
t
PLBX
t
BVPH
t
XLWL
t
WLBX
t
BVWL
WLRL
XTAL1
PAGEL
t
PLXH
XLXH
t
t
XLPH
ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte)
DATA
BS1
XA0
XA1
LOAD ADDRESS
(LOW BYTE)
LOAD DATA
(LOW BYTE)
LOAD DATA
(HIGH BYTE)
LOAD DATA
LOAD ADDRESS
(LOW BYTE)