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2.3 Operation Status Register Group
The operational status register group consists of three 16-bit registers: status register, event register, and enable register.
When the status register corresponding bit is changed, the corresponding event register bit will be set. If the corresponding
bit in the enable register bit is set, it will be generated once Event (status byte register OPER is set). After executing an
event register read operation, the event register will be automatically cleared. The status register is dened as follows:
Bit Signal Description
Bit0 CAL The electronic load is calculated a new calibration constant.
Bit5 WTG The electronic load is waiting for a trigger.
2.4 Status Byte Register Group
The status byte register group consists of two 8-bit registers: event register and enable register. If the corresponding bit
in the enable register bit is set, it will be generated once Event (status byte register RQS is set). The status byte register
will be automatically cleared when an event register read is executed. The status register is dened as follows:
Bit Signal Description
Bit3 QUES Indicates if an enabled questionable event has occurred.
Bit4 MAV Indicates if the Output Queue contains data.
Bit5 ESB Indicates if an enabled standard event has occurred.
Bit6 RQS During a serial poll, RQS is returned and cleared.
Bit7 OPER Indicates if an operation event has occurred.
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