Freescale Semiconductor MC68332 - Page 15

MC68332
USER’S MANUAL
(Continued)
Figure Title Page
LIST OF ILLUSTRATIONS
6-3 QSPI RAM ...................................................................................................... 6-8
6-4 Flowchart of QSPI Initialization Operation .................................................... 6-11
6-5 Flowchart of QSPI Master Operation (Part 1) .............................................. 6-12
6-5 Flowchart of QSPI Master Operation (Part 2) .............................................. 6-13
6-5 Flowchart of QSPI Master Operation (Part 3) .............................................. 6-14
6-6 Flowchart of QSPI Slave Operation (Part 1) ................................................ 6-15
6-6 Flowchart of QSPI Slave Operation (Part 2) ................................................ 6-16
6-7 SCI Transmitter Block Diagram .................................................................... 6-23
6-8 SCI Receiver Block Diagram ........................................................................ 6-24
7-1 TPU Block Diagram ........................................................................................ 7-1
7-2 TCR1 Prescaler Control ............................................................................... 7-12
7-3 TCR2 Prescaler Control ............................................................................... 7-13
A-1 CLKOUT Output Timing Diagram .................................................................A-14
A-2 External Clock Input Timing Diagram ...........................................................A-14
A-3 ECLK Output Timing Diagram ......................................................................A-14
A-4 Read Cycle Timing Diagram ........................................................................A-15
A-5 Write Cycle Timing Diagram .........................................................................A-16
A-6 Fast Termination Read Cycle Timing Diagram ............................................A-17
A-7 Fast Termination Write Cycle Timing Diagram .............................................A-18
A-8 Bus Arbitration Timing Diagram —Active Bus Case ....................................A-19
A-9 Bus Arbitration Timing Diagram — Idle Bus Case .......................................A-20
A-10 Show Cycle Timing Diagram ........................................................................A-20
A-11 Chip Select Timing Diagram .........................................................................A-21
A-12 Reset and Mode Select Timing Diagram ......................................................A-21
A-13 Background Debugging Mode Timing Diagram — Serial Communication ...A-23
A-14 Background Debugging Mode Timing Diagram — Freeze Assertion ...........A-23
A-15 ECLK Timing Diagram ..................................................................................A-25
A-16 QSPI Timing — Master, CPHA = 0 ..............................................................A-27
A-17 QSPI Timing — Master, CPHA = 1 ..............................................................A-27
A-18 QSPI Timing — Slave, CPHA = 0 ................................................................A-28
A-19 QSPI Timing — Slave, CPHA = 1 ................................................................A-28
A-20 TPU Timing Diagram ....................................................................................A-29
B-1 132-Pin Plastic Surface Mount Package Pin Assignments ............................B-2
B-2 144-Pin Plastic Surface Mount Package Pin Assignments ............................B-3
D-1 User Programming Model ..............................................................................D-2
D-2 Supervisor Programming Model Supplement .................................................D-2
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Freescale Semiconductor, Inc.
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