Hioki 3227 - Status Byte Register

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8.3 Introduction for the GP-IB
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8
.3.11 Status Byte Register
bit 7
bit 5
bit 4 bit 3 bit 2 bit 1 bit 0
Unuse
d
ESB MAV Unuse
d
Unuse
d
Unuse
d
Unuse
d
bit 6
RQS
MSS
Logical sum
&
&
bit 7 bit 6
bit 5
bit 4 bit 3 bit 2 bit 1 bit 0
Unuse
d
× ESB MAV Unuse
d
Unuse
d
Unuse
d
Unuse
d
Status byte register (STB
)
Service request enable register (SRER
)
・・・
Bit 7 Unused
Bit 6
RQS
MSS
Set to 1 when a service request is dispatched
Logical sum of the other bits of the status byte register
Bit 5 ESB
Standard event summary (logical sum) bit
Bitwise logical sum of the standard event status register
Bit 4 MAV
Message available
Indicates that there are some messages in the output queue
Bit 3 Unused
Bit 2 Unused
Bit 1 Unused
Bit 0 Unused
(1) Status byte register (STB)
The status byte register is an 8-bit register whose contents are output from
the 3227 to the controller, when the serial polling is being performed.
If even only one bit in the status byte register has changed from 0 to 1
(provided that it is a bit which has been set in the service request enable
register as a bit which can be used), then the MSS bit is set to 1.
Simultaneously with this RQS bit is set to 1, and a service request is
generated.
The RQS bit is always synchronized with the service requests, and only read
out and simultaneously cleared when the serial polling is being performed.
Although the MSS bit is only read out on a "*STB?"query, but it is
not cleared until the event is cleared by a "*CLS" command.
Status byte register bit assignments
(2) Service request enable register (SRER)
When each bit of the service request enable register is set to 1, the
corresponding bit of the status byte register becomes able to be accessed.