Hioki 3227 - Event Register

76
────────────────────────────────────────────────────
8.3 Introduction for the GP-IB
────────────────────────────────────────────────────
8
.3.12 Event Register
bit 5
ESB
bit 6
RQS
MSS
Logical sum
& & & & &
& & &
Status byte register (STB
)
Standard event status enable register (SESER
)
Standard event status register (SESR
)
bit 7 bit 6
bit 5
bit 4 bit 3 bit 2 bit 1 bit 0
PON URQ CME EXE DDE QYE RQEC OPC
bit 7 bit 6
bit 5
bit 4 bit 3 bit 2 bit 1 bit 0
PON URQ CME EXE DDE QYE RQEC OPC
・・・ ・・・ ・・・ ・・・ ・・・ ・・・ ・・
・
(1) Standard event status register (SESR)
The standard event status register is an 8-bit register. If any bit in the
standard event status register is set to 1 (after masking by the standard event
status enable register), bit 5(ESB) of the status byte register is set to 1.
The standard event status register is cleared in the following three situations.
When the "＊CLS" command is received.
When the "＊ESR?" query is received.
When the power is turned on again.