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8.3 Interface Outline
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8.3.12 Status Byte Register
bit 7
bit 5
bit 4 bit 3 bit 2 bit 1 bit 0
Unused
ESB MAV
Unused
ESB2 ESB1 ESB0
bit 6
SRQ
MSS
bit 7 bit 6
bit 5
bit 4 bit 3 bit 2 bit 1 bit 0
Unused
×
ESB MAV
Unused
ESB2 ESB1 ESB0
Status byte register (STB)
Service request enable register (SRER)
Logical sum
&
& & & & &
・・・ ・・・・・・・・・・・ ・・・
Status byte register bit assignments
Bit 7
Unused.
Bit 6
SRQ
Set to 1 when a service request is dispatched.
MSS
Logical sum of the other bits of the status byte register
Bit 5
ESB
Standard event summary (logical sum) bit
Shows a logical sum of the standard event status register.
Bit 4
MAV
Message available.
Indicates that there is at least one message in the output queue.
Bit 3
Unused
Bit 2
ESB2
Event summary (logical sum) bit2
Shows a logical sum of the standard event status register 2.
Bit 1
ESB1
Event summary bit 1
Bitwise logical sum of event status register 1
Bit 0
ESB0
Event summary bit 0
Bitwise logical sum of event status register 0
(1) Status byte register (STB)
The status byte register is an 8-bit register whose contents are output from
the 3332 to the controller, when serial polling is being performed.
If even only one bit in the status byte register has changed from 0 to 1
(provided that it is a bit which has been set in the service request enable
register as a bit which can be used), then the MSS bit is set to 1.
Simultaneously with this the SRQ bit is set to 1, and a service request is
generated.
The SRQ bit is synchronized with service requests, and is read out and
simultaneously cleared when serial polling is being performed. Although the
MSS bit is only read out on an "
*
STB?" query, on a "
*
CLS" command for
example it is not cleared until the event is cleared.
(2) Service request enable register (SRER)
This register masks the status byte register. Setting a bit of this register to 1
enables the corresponding bit of the status byte register to be used.
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