Hioki 3332 - Event Registers

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8.3 Interface Outline
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8.3.13 Event Registers
bit 5
ESB MAV
SRQ
MSS
Logical sum
& & & & &
& & &
Status byte register (STB)
Standard event status enable register (SESER)
Standard event status register (SESR)
bit 7 bit 6
bit 5
bit 4 bit 3 bit 2 bit 1 bit 0
PON URQ CME EXE DDE QYE RQC OPC
bit 7 bit 6
bit 5
bit 4 bit 3 bit 2 bit 1 bit 0
PON URQ CME EXE DDE QYE RQC OPC
・・・ ・・・ ・・・ ・・・ ・・・ ・・・ ・・・
(1) Standard event status register (SESR)
The standard event status register is an 8-bit register. If any bit in the
standard event status register is set to 1 (after masking by the standard event
status enable register), bit 5 (ESB) of the status byte register is set to 1.
The standard event status register is cleared in the following three situations:
① When a "
*
CLS" command is received.
② When an "
*
ESR?" query is received.
③ When the unit is powered on.