Within each set
the
top
row
of
each character
is
the first 256
bytes, the second
row
in
the
next 256, etc. Within each byte the
high order bit 7
is
displayed on the left side
of
the character. A 1
is
stored
for
a lit dot, a 0
for
an
unlit dot.
The complete address definiton
of
the
ROM
is:
A13 A12 A11,10,9,8 A7,6,5,4,3,2,1,0
Row
# Character CodeFont Height
0=
STD
0=
8x8
1 =
HP
1 = 14x8 Row 0
is
the
top
of
the cell.
RAM
Access
The HP45981A contains 32K
of
RAM
based
in
a contiguous
segment
B8000-BFFFF.
The 'memory on the video card
is
run
asynchronously
to
the 80286. Therefore, any
access
to
the video
memory will include at least
four
wait-states, and
as
many
as
six
wait-states
to
complete
an
instruction.
Refresh
is
generated
internally. Data
is
taken from memory depending on the mode
of
operation. The
two
modes
of
operation
are:
alpha mode and
graphics mode.
Memory address wrapping and page selection
is
controlled by
four
bits
in
the extension control register.
The
16/32K select (bit 4)
and the page select (bit
5)
determine the way the
SPU
has
access
to
memory. The vertical resolution (bit
0)
and the
font
select (bit
2)
determine the way the display
accesses
the memory. The
access
to
memory differs in the alpha and graphics modes. The various
access
methods are summarized in the following table:
86 Multi-Mode Video Adapter
Card
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