HP Vectra User Manual

Table 2.5
36-Pin Connector Assignments
Circuit Side
Component Side
Pin
I/O Signal Name Pin I/O
Signal
Name
D1
I
-MEM
C516
C1
I/O
5BHE
D2
I -I/O C516
C2
I/O
LA23
D3 I
IRQ10 C3
I/O
LA22
D4 I
IRQ11 C4
I/O
LA21
D5 I
IRQ12
(5
I/O
LA20
D6
I IRQ15
C6
I/O
LA19
D7 I
IRQ14 C7
I/O
LA18
D8
0
-DACKO
C8
I/O
LA17
D9
I DRQO
(9
I/O
-MEMR
D10
0 -DACK5
C10
I/O
-MEMW
D11
I DRQ5 C11
I/O
5D8
D12 0 -DACK6
C12
I/O
5D9
D13
I DRQ6
C13
I/O
5D10
D14 0
-DACK7
C14
I/O
5D11
D15 I
DRQ7
(15
I/O
SD12
D16
+ 5Vdc
C16
I/O
5D13
D17 I
-
MASTER
(17
I/O
SD14
D18
GND
(18
I/O
SD15
I/O Signal Descriptions
Signal
AEN
BALE
I/O Description
o This signal is used to inform the system
that the DMA controller has control of the
address and control buses. This signal is
active during DMA transfers.
o This is the buffered ALE signal from the
82288 bus controller. Its falling edge
indicates valid address and control signals.
BALE is forced high during DMA cycles.
Processor Board 31

HP Vectra Specifications

General

Processor	Intel Pentium
RAM	Up to 128 MB
Storage	HDD (capacity varies by model)
Operating System	Windows 95
Graphics	Integrated
Ports	Serial, Parallel
Expansion Slots	ISA, PCI