System Performance
The
HP
Vedra
PC
employs a 16 MHz clock
to
drive the 80286 at 8
MHz. There
is
a 14.318 MHz clock
used
to
provide a timing clock
for
the
I/O
bus and the system timer/counter. The 14.318 MHz
clock
has
a variable capacitor
for
fine tuning.
The 80286 requires
two
clock
cycles
(SYSCLK)
to
complete a bus
cycle.
With
an
8 MHz clock, this translates into a 250ns bus cycle
time.
This
bus
cycle
time
is
too
fast
for
many memory and
I/O
devices, therefore, wait-states are inserted. The processor board
is
configured
to
insert one wait-state
in
every bus cycle. This extends
the bus cycle time
to
375ns, allowing standard memory devices
sufficient time.
This
is
the bus cycle time
for
all
16-bit transfers,
either
I/O
or memory.
Any transfer
to
an
8-bit device requires additional wait-states. The
number
of
extra wait-states depends on the setting
of
jumper
JU2
on the processor board. It
has
two
positions and may
be
set
for
four
or
five wait-states (including the one normally inserted)
for
each 8-bit transfer. Figure 7 shows the configuration settings
for
JU2.
Processor Board 15
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