The
jumper
E3, E2,
E1
selects
the
location
of
the
interface
registers in
the
system
I/O
map. Placing a shunt between
E3
and
E2
selects
the
primary addressing,
3FOH
through
3F7H
(operational state-default). Placing a shunt between E1 and
E2
selects
the
secondary addressing, 370H through 377H.
The
jumper
E7,
E8
closes
the
phase lock loop
(PLL)
feedback path.
The operational state
is
with
a shunt between
E7
and
E8,
which
closes
the
feedback path. The removal
of
this shunt allows
adjustments
to
the
PLL
and
is
not
the
operational state.
Foe
Function
The flexible disc controller subsystem
is
responsible for: generating
various signals needed
to
control
the
electromechanical parts
of
the
drive, interpreting
the
status signals received from
the
drive,
and converting between parallel and serial data formats. It
is
centered around
the
NEC
765A
flexible disc controller
(FDC)
chip.
The
FDC
chip converts parallel data from the 80286
to
serial data
for
the
write
path, and inversely, converts serial data from
the
read path
to
parallel data
for
the
80286. The
FDC
chip transfers
parallel data
to
and
from
the
system memory space
via
DMA
(Channel
2).
Commands
to
the
FDC
chip and status information
from
it
are transferred
via
programmed
I/O.
Command
termination and error conditions are signaled
through
interrupts
(IRQ6).
The subsystem employs
an
analog phase locked loop
(PLL)
to
generate a clock synchronous
to
the
disc data.
This
clock
is
used by
the
FDC
chip during disc read transfers. The
PLL
can
operate at 250kHz, 300kHz,
or
500kHz data rates. The data rates
are selected via
the
digital control port.
System-to-Subsystem Interface
The flexible disc controller subsystem interfaces
with
the
microprocessor
through
six
registers. There are three
write
registers and three read registers. The following table lists
the
registers and their primary and secondary
1/0
addresses.
46
Processor Board
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