HP Vectra

Table 2.10
Accessible Registers
Register
Digital Output Register
Digital Control Register
FDC Data Register
FDC Status Register
Digital
Input Register
Digital Output Register
RIW
w
W
RIW
R
R
I/O Address
Primary Secondary
3F2 372
3F7 377
3F5 375
3F4 374
3F7 377
Bit Data Definition
7 Reserved
6
Reserved
5 Drive B motor enable, active high turns on motor
5 1 /4" drive
4
Drive A motor enable, active high turns on motor
5 1 /4" drive
3 Interrupt and
DMA enable, activ high
2
FDC reset, active low will reset
Reserved
0
0
Drive select, Drive A
Drive B
Processor Board 47