HP Vectra

RAM Organization
BANKS DATA BITS PARITY BIT
t
00000
64K x 4 64K x 4
64K x 1
256K
01000
MIN
02000
•
03000
~ ~
04000
05000
06000
EXPANSION
07000
08000
09000
r
09FFF
Figure 6
Refresh Cycles
The refresh controller operates from the 8 MHz system clock. A
RAM refresh occurs approximately once every 16us. Each refresh
cycle requires five system clock cycles.
Parity
Parity is generated for each byte of RAM during write operations,
and checked during read operations. If a parity error occurs,
the
Processor Board 11