HP Vectra User Manual

Signal
-OWS
I/O Map
I/O Description
I This signal indicates to the system that a
read
or write operation can take place
without additional system generated wait-
states. To perform a 16-bit memory cycle
with zero wait-states, this signal should be
asserted
as soon as a valid address decode
and a read
or write command is detected.
To shorten cycles
for 8-bit devices, - OWS
should be asserted on the falling edge of
SYSCLK after detecting a valid address
and a read
or write command for two
wait-states. If asserted on the second
falling edge
of SYSCLK after detecting a
valid address and a read
or write
command, three wait-states will be
generated
for 8-bit devices. The driver
should be
an open collector or a tri-state
device capable
of sinking 20ma.
The
HP Vectra uses the first 1024 I/O port addresses, OOOH
through 3FFFH. Note that ports OOOH through OFFH are reserved
for I/O on the processor board and ports 100H through 3FFH are
available
to adapters connected to the seven I/O channel
connectors. The one exception
to this is the flexible disc controller
subsystem. which uses either I/O ports 3FOH through 3F7H (when
configured for its primary address) or I/O ports 370H through
377H (when configured for its secondary address), even though it
resides on
the processor card.
36 Processor Board

HP Vectra Specifications

General

Processor	Intel Pentium
RAM	Up to 128 MB
Storage	HDD (capacity varies by model)
Operating System	Windows 95
Graphics	Integrated
Ports	Serial, Parallel
Expansion Slots	ISA, PCI