HP Vectra

The following table defines the interrupt priorities.
Table
11.3
Interrupt Priority
Interrupt Priority Interrupt Source
Clear Interrupt
Receiver line 1 Overrun error or
Reading the line
status
parity error
or status register.
framing error
or
break (200mS
space on receive
data line).
Received
2
Data available in Reading the
data
receive buffer. receive buffer
available
register.
Transmitter
3 Data transmitted
Reading the
buffer
from transmit
interrupt
register buffer. identification
empty register (if
source),
or
writing to the
transmit buffer
register.
Modem
4 CS, CC, CE or CF
Reading the
status signal received.
modem status
register.
128 Serial/Parallel Card