Table 2.2
Wait-State Generation
TRANSFER POSITION 1
POSITION 2
NORMAL
TYPES WAIT-STATES
WAIT-STATES
CYCLES TOTAL
16
to 16
1
1
2
3
8 to 8
4
5
2
6
or
7*
16
to
8 8
10
4
12
or
14*
8 to 16 8
10
4
12
or
14*
The
HP
Vectra
PC
has
provisions
to
maximize system performance
wh,en
fast memory and
I/O
devices are installed
in
the
I/O
channel
connectors. The --
OWS
signal may be asserted by a peripheral
to
signal the processor board
to
insert fewer wait-states. If this signal
is
asserted during a transfer
to
a 16-bit device, no wait-states will
be
inserted. If it
is
asserted during a transfer
to
an
8-bit device,
either
two
or
three wait-states will
be
inserted, depending on the
timing
of
the assertion.
*Depends on setting
of
JU2.
Processor Board 17
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