System Timers/Counters
The
HP
Vectra
PC
contains the Intel 8254 timer/counter device
which provides three independent 16-bit counters.
The
input
frequency
of
1.19MHz
is
derived from the 14.318 MHz system
timing clock. The minimum time resolvable
is
approximately 838
nanoseconds
(1
input clock cycle), and the maximum
is
55
milliseconds (65,536 clock
cycles).
All three timers have dedicated system
uses.
Timer 0
is
used
to
generate the real-time clock interrupt. Counter 1
is
dedicated
to
RAM refresh. No attempt should
be
made
to
reprogram this
channel. Counter 2
is
used
to
drive the speaker.
Counter 2
has
a Gate input which
is
under program control. This
Gate input
is
Bit 0
of
"Port B"
(61
H).
Setting this bit
to
0 inhibits
counting action, effectively turning the speaker off.
In
addition,
bit 1
is
"AND"ed
with
the timer output; writing a 0
also
disables
the speaker. The following
is
a block diagram
of
the timer.
Timer Block Diagram
+5V
...........
60
1.19
MHz
COUNTER
----~
IRQ 0
o (SYSTEM TIMER)
7
6
PORT
8
(61
H)
61
.....
--4
COUNTER
1
.....-......-_
... 62
-.-..-___.
COUNTER
2
Figure 8
..----II~
RA
M
REFRESH
REQUEST
18
Processor
Board
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