HP Vectra

The following table defines the port addresses for the DMA
controller.
Table 2.3
DMA Port Assignments
PORT
ADDRESS Ie REGISTER
OOOOH DMA # 1
Ch 0 Address
0OO1H Ch 0 Count
0OO2H Ch 1 Address
0OO3H
Ch 1 Count
0OO4H Ch 2 Address
OOOSH Ch 2 Count
0OO6H Ch 3 Address
0OO7H Ch 3 Count
0OO8H Read StatuslWrite Command
0OO9H Write Request
OOOAH Write Single Mask Register Bit
OOOBH
Write Mode Register
OOOCH Clear Byte Pointer Flip-flop
OOODH
Read Temporary ReglWrite
Master
Clear
OOOEH
Clear Mask Register
OOOFH
Write All Mask Register Bits
0081H Page Reg
Channel 2 A 16 - A23
0082H
Channel 3 A 16 - A230083H
0083H
Channel 1 A 16 - A23
0087H
Channel 0 A 16 - A23
0089H
Channel 6 A 17 - A23
008AH
Channel 7 A 17 - A23
008SH
Channel 5 A 17 - A23
008FH Refresh
26 Processor Board