PORT
ADDRESS
OOCOH
OOC2H
OOC4H
OOC6H
OOC8H
OOCAH
OOCCH
OOCEH
OODOH
OOD2H
OOD4H
OOD6H
OOD8H
OODAH
OC)DCH
OODEH
Ie
DMA#
2
REGISTER
Ch
4 Address
Ch
4 Count
Ch
5 Address
Ch
5 Count
Ch
6 Address
Ch
6 Count
Ch
7 Address
Ch
7 Count
Read
Status /
Write
command
Write Request
Write Single Mask Register Bit
Write
Mode
Register
Clear Byte Pointer Flip-flop
Read
Temporary ReglWrite
Master Clear
Clear Mask Register
Write All Mask Register Bits
Note,
the
I/O ports
for
DMA
controller
1
(for
8-bit
transfers) are
located on consecutive addresses,
while
the
ports
for
controller
2
are
on
even-byte addresses. All registers should be loaded
with
valid parameters
after
power-up
or
reset. This should be
done
even
if
some channels are unused.
Processor Board 27
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