Line Control Register (XFBH)
This
register controls the format
of
the data communications.
Bit
Data Definition
0-1
Specifies the number
of
bits
in
each transmitted
or
received character
as
in the following:
Bit Character Length
o 1
in
bits
1 1
8
1 0 7
o 1 6
o 0
5
2
0
One stop bit
is
generated or deleted
in
the data sent
or received.
1 1/2 stop bit
is
generated or deleted
for
5-bit
words.
For
a
6,
7,
or 8-bit word, 2 stop bits are
generated or deleted.
,.
3
0 Disable parity bit.
1 A parity bit
is
generated (transmit data)
or
deleted
(receive data).
4 0 When bit 3
is
1,
parity bits sent
or
checked odd.
1
When bit 3
is
1,
parity bits sent
or
checked even.
5
When bit 3
is
1,
the parity bit
is
set 0
for
even parity
and 1 for odd parity.
0
Stuck parity disabled.
6
Break bit.
The
transmit data line
is
set
to
the space
state
(0)
and remains at
that
state regardless
of
the
state
of
the
output
buffer register.
0 Set-breaking
is
disabled.
7
Address selection bit.
Set
to
gain
access
of
the
r-
divisor latches
of
the baud-rate generator during a
read/write operation.
0
Reset
to
gain
access
of
the receiver buffer register,
the transmit buffer register,
or
the interrupt enable
register.
Serial/Parallel
Card
129
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