Signal
I/O
Description
SDO-SD15
I/O
This
is
the
system data bus. Data
is
transferred
to
and
from
the
system on
these lines. Sixteen-bit transfers occur on
~
SDO-SD15.
Eight-bit transfers occur on
SDO-SD7,
unless
SBHE
is
asserted.
In
which
case,
data
is
transferred on
SD8-
SD15. Sixteen-bit
to
8-bit transfers are
multiplexed by
the
backplane state
machine
into
two
8-bit transfers on
SDO-
SD7.
-SMEMR
0
These signals indicate a memory read
-MEMR
I/O
cycle
is
progress. MEMR may be driven by
a
DMA
controller
or
by an external
microprocessor (if
MASTER
is
asserted).
- SMEMR
is
active
if
- MEMR
is
active
and
the
address decode circuit indicates a
valid address in
the
bottom
1
Mbyte
of
memory space. Both
of
these signals are
active low.
r
-SMEMW
0
These signals indicate a memory
write
-MEMW
I/O
cycle
is
in progress. -
MEMW
may be
driven by a
DMA
controller
or
by an
external microprocessor (if
MASTER
is
asserted). - SMEMW
is
active
if
-
MEMW
is
active and
the
address decode circuit
indiactes a valid address in
the
bottom
1
Mbyte
of
memory space. Both
of
these
signals are active low.
SYSCLK
0 This
is
the
8
MHz
processor system clock.
It
has
a
50%
duty
cycle and a period
of
approximately 125
ns.
This signal can be
used
to
synchronize activities
to
the
80286.
,..
T/C
0
This signal informs
the
system
that
the
terminal
count
for
one
of
the
DMA
channels
has
been reached. The signal
is
active high.
Processor Board 35
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