Signal
I/O Description
-MEM
CS16
I This signal
is
used
to
indicate
to
the
system
that
the
adapter board can
perform 16-bit memory operations. The
driver should be
an
open collector
or
a tri-
state device capable
of
sinking 20ma. This
signal should be derived
from
LA
17 -
LA23.
OSC
0
This
is
a 14.318 MHz timing reference
signal. It
has
a 50
0
/0
duty
cycle and a
period
of
approximately 70
ns.
This signal
is
asynchronous
with
the
SYSCLK.
-
REFRESH
I/O This signal indicates a memory refresh
operation
is
in progress. This signal may
be driven by a processor on
the
I/O
channel. This signal
is
active low.
RESET
DRV
0 This signal
is
used
to
reset all system
devices during power-on resets and
indicate
low
line-voltage conditions. The
~
signal
is
active high.
SAO-SA
19
I/O These are
the
system address lines.
When
combined
with
LA
17-LA23 they produce
16 Mbytes
of
memory address space.
SAO-SA
19 begin
to
change on
the
rising
edge
of
BALE,
and are latched
for
the
duration
of
the
cycle by
the
falling edge
of
BALE.
SAO-SA
19 may be driven by a
DMA
controller
or
processor on
the
I/O
channel. The system refresh controller
places
the
refresh address on
SAO-SA7
during refresh cycles.
SBHE
I/O
This signal indicates
that
data
is
to
be
transfered on SD8-SD15.
SBHE
indicates a
16-bit transfer
or
an
8-bit transfer
to
an
~
odd
address
(AD
=
1)
is
progress.
34
Processor Board
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