The JTAG port has the highest priority and overrides the MSEL pin settings. Consequently, you can configure the Intel Agilex
device over JTAG even if the MSEL pins specify a different configuration scheme unless you disabled JTAG for security reasons.
CvP
CvP uses an external PCIe* host device as a Root Port to configure the Intel Agilex device over the PCIe link. You can specify
up to a x16 PCIe link. Typically, the bitstream compression ratio and the SDM input buffer data rate, not the PCIe link, limit
the configuration data rate Intel Agilex devices support two CvP modes, CvP init and CvP update.
CvP initialization process includes the following two steps:
1. CvP configures the FPGA periphery image which includes I/O information and hard IP blocks, including the PCIe IP. CvP
uses quad SPI memory and AS x4 to configure the peripheral image. Because the PCIe IP is in the periphery image, PCIe
link training establishes the PCIe link of the CvP PCIe IP before the core fabric configures.
2. The host device uses the CvP PCIe link to configure your design in the core fabric.
CvP update mode updates the FPGA core image using the PCIe link already established from a previous full chip configuration
or CvP init configuration. After the Intel Agilex enters user mode, you can use the CvP update mode to reconfigure the FPGA
fabric. This mode has the following advantages:
• Allows reprogramming of the core to run different algorithms.
• Provides a mechanism for standard updates as a part of a release process.
• Customizes core processing for different components that are part of a complex system.
For both CvP Init and CvP Update modes, the maximum data rate depends on the PCIe generation and number of lanes.
For Intel Agilex SoC devices, CvP is only supported in FPGA configuration first mode.
AS Normal Mode
Active Serial x4 or AS x4 or Quad SPI is an active configuration scheme that supports flash memories capable of three- and
four-byte addressing. Upon power up, the SDM boots from a boot ROM which uses three-byte addressing to load the
configuration firmware from the Quad SPI flash. After the configuration firmware loads, the Quad SPI flash operates using
four-byte addressing for the rest of the configuration process.
AS Fast Mode
The only difference between AS normal mode and fast mode is speed. Use AS fast mode when configuration timing is a
concern. This mode does not delay for 10 ms before beginning configuration. Use this mode to meet the 100 ms of power up
requirement for PCIe or for other systems with strict timing requirements.
1. Intel
®
Agilex
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Configuration User Guide
UG-20205 | 2019.10.09
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Configuration User Guide
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