System Management
222
Basic System Configuration Guide
3HE 11010 AAAC TQZZA Edition: 01
On the 7705 SAR-18, either BITS port 1 or port 2 is available as an input and output
source. When both inputs are connected and available, then the quality level (QL)
from Synchronization Status Messaging (SSM) is used to determine which port is
used by the CSMs as the BITS input. If SSM is not available, then BITS port 1 is the
preferred input. BITS port 2 is used if BITS port 1 is not available. In this case, the
operation is non-revertive. The BITS output ports 1 and 2 are clocked by the active
CSM’s SSU clock.
The BITS output source command can be used to configure the BITS output ports’
source path on the 7705 SAR-18 to be either:
• the filtered clock from the Synchronous Equipment Timing Generator (SETG)
• the alternate unfiltered path from the BITS output port via Selector A and C, as
per ITU-T G.8262
Figure 11 shows an example of a timing source path. The BITS port is configured to
deliver an input reference directly to a dedicated timing device such as a BITS or
standalone synchronization equipment (SASE) device in a customer facility. The
external BITS clock can have multiple references and can provide a common high-
quality clock to all network elements at the customer location, including the
7705 SAR-18 node.
Figure 11 BITS Timing Source Path
BITS
Selector
B
Selector
A
TE
T3
T2
T1
SETG
SEC/EEC
SETS
Network Element
Ethernet,
SDH
BITS-input
Network timing
reference
BITS-output
T0
T0
Ethernet
SDH
PDH
EXT
Selector
C
Network reference from other equipmentTiming references to other CO equipment
Unfiltered Network timing path
Filtered Inter-office timing path
Network timing reference
Legend:
26624
To Next Page
Loading...
