System Management
234
Basic System Configuration Guide
3HE 11010 AAAC TQZZA Edition: 01
Each PTP slave clock can be configured to receive timing from up to two PTP master
clocks in the network.
IEEE 1588 PTP messaging for slave and master clocks is supported over module
ports on the 7705 SAR-M and 7705 SAR-H, on Ethernet ports on the 7705 SAR-A,
7705 SAR-Ax, 7705 SAR-W, and 7705 SAR-Wx, and on all of the adapter cards
listed in Table 26.
When a node loopback address is used as the source interface for 1588 packets, the
packets can ingress and egress the module ports. Module ports do not support
transparent clock, except for the 2-port 10GigE (Ethernet) module which does.
For all 7705 SAR platforms and clock types, when the node loopback address is
used as the source interface for 1588 packets, the packets can ingress and egress
over IES interfaces.
IP messaging between the PTP master clock and PTP slave clock over the
PTP-enabled IP interface is done using IPv4 unicast mode.
Each PTP instance supports up to 128 synchronization messages per second. The
default is 64 synchronization messages per second when the profile is set to the
default of ieee1588-2008.
Each master clock has its own configuration for IP address, packet rate, and
messaging timeouts, and for statistics, alarms, and events. Each available master
clock advertises its presence and information using announce messages. If both
master clocks are available, the slave clock uses the Best Master Clock Algorithm
(BMCA) to dynamically compare the information in the announce messages of each
master clock to determine to which of the two master clocks it should synchronize.
This master clock is known as the best master. After the slave clock has determined
which is the best master, it may begin to negotiate with it for unicast synchronization
communication.
The configured setting for the profile command determines the precedence order for
selecting the best master clock algorithm. The 7705 SAR supports the following
profile settings: ieee1588-2008, itu-telecom-freq, and g8275dot1-2014. For
information about the g8275dot1-2014 profile parameter, see ITU-T G.8275.1.
If the profile setting for the clock is ieee1588-2008, the precedence order for the best
master selection algorithm is as follows:
• priority1 (user-configurable on the master clock side)
• clock class
• clock accuracy
• PTP variance (offsetScaledLogVariance)
• priority2 (user-configurable on the master clock side)
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