Nvidia JETSON XAVIER NX

NVIDIA Jetson Xavier NX DG-09693-001_v1.7 | xi
Table 12-2. I2C Interface Signal Routing Requirements ....................................................... 69
Table 12-3. I2C Signal Connections ........................................................................................ 69
Table 12-4. SPI Pin Descriptions............................................................................................. 70
Table 12-5. SPI Interface Signal Routing Requirements ....................................................... 71
Table 12-6. SPI Signal Connections ........................................................................................ 72
Table 12-7. UART Pin Descriptions ......................................................................................... 72
Table 12-8. UART Signal Connections .................................................................................... 73
Table 12-9. CAN Pin Descriptions ........................................................................................... 74
Table 12-10. CAN Interface Signal Routing Requirements ..................................................... 74
Table 12-11. CAN Signal Connections ...................................................................................... 75
Table 12-12. Fan Pin Descriptions ............................................................................................ 75
Table 12-13. Debug UART Pin Descriptions ............................................................................. 76
Table 12-14. Debug UART Connections .................................................................................... 76
Table 13-1. Pins Pulled or Driven High by Xavier Prior to SYS_RESET* Inactive ................. 79
Table 13-2. Pins with External Pull-ups to Supply on before SYS_RESET* Inactive ........... 80
Table 14-1. Unused MPIO Pins and Pin Group ....................................................................... 81
Table 18-1. Signal Type Codes ................................................................................................ 86
Table 18-2. Common High-Speed Interface Requirements .................................................. 89