NVIDIA Jetson Xavier NX DG-09693-001_v1.7 | iii
Updated Section 5.2 “PCIe”
• Updated Figure 5-9 and the note to include open-drain buffers on the
control signals when NX is an Endpoint
• Updated the notes to Table 5-9
• Updated Table 5-10
• Updated eDP and DP pin descriptions in Table 6-1
• Removed series resistor after the level shifter and added related note
to Figure 6-1
• Removed resistor divider on HPD in Figure 6-7
• Removed GPIO08 for card select mention in Table 8-1
• Updated Figure 8-1 with the following: moved load switch enable to
GPIO, moved card detect to generic GPIO, and removed series
resistor on card detect line
• Updated Table 8-3 with generic GPIO
• Replaced FET circuit used for level shifters with generic level shifter
blocks in Figure 10-7
• Removed design checklist and pin descriptions tables and made
them separate attachments to this design guide
1.0 April 21, 2020
• Added note to Table 4-1 regarding direction of CLK_32K_OUT signal
• Added note to Table 5-2 regarding PEX_L4_RST* and PCIE_WAKE*
signals
• Updated Section 5.2 on PCIe
• Added Table 5-10 on PCIe Gen4 routing requirements
• Added note to Table 6-1 regarding DP_AUX_CH[1:0]_HPD direction
• Added note to Table 7-2 regarding CAM[1:0]_MCLK and
CAM[1:0]_PWDN direction
• Added note to Table 8-1 regarding SDMMC_CLK direction
• Added note to Table 9-1 regarding I2S[1:0]_DOUT and _DIN direction
• Added note to Table 10-7 regarding UART pins
• Updated Figure 10-5 to show on module buffers and added related
note
• Added note to Table 10-9 regarding CAN signals
• Added note to Table 10-12 regarding GPIO014 and GPIO008 direction
Updated attachments
1.1 May 7, 2020
Updated Table 5-5 with the following:
Updated Gen1 and Gen2 values
Removed redundant GND via reference requirement and
accompanying note
Added Gen2 specific requirements to ESD
• Updated Table 6-5 with max trace lengths (more relaxed) and PTH
vias (more restrictive)
• Updated Table 7-4 with the following:
Removed max loading spec
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