NVIDIA Jetson Xavier NX DG-09693-001_v1.7 | viii
List of Figures
Figure 2-1. Jetson Xavier NX Block Diagram ........................................................................... 4
Figure 4-1. Jetson Xavier NX Module Installed in SODIMM Connector .................................. 9
Figure 4-2. Module to Connector Assembly Diagram ........................................................... 10
Figure 5-1. System Power and Control Block Diagram ........................................................ 13
Figure 5-2. Power Up Sequence (No Power Button – Auto Power On) ................................ 14
Figure 5-3. Power Up Sequence (With Power Button) .......................................................... 14
Figure 5-4. Power Down (Initiated by SHUTDOWN_REQ* Assertion) ................................... 15
Figure 5-5. Power Down (Initiated by POWER_EN De-assertion) ........................................ 15
Figure 5-6. Power Down (Sudden Power Loss) ..................................................................... 16
Figure 6-1. USB 3.2 Micro B USB Device and Recovery Connection Example .................... 20
Figure 6-2. USB 3.2 Type A Host Only Connection Example ................................................. 20
Figure 6-3. IL/NEXT Plot (GEN1) ............................................................................................. 23
Figure 6-4. IL/NEXT Plot (GEN2) ............................................................................................. 24
Figure 6-5. Via Topology .......................................................................................................... 24
Figure 6-6. Component Order ................................................................................................. 24
Figure 6-7. Component Placement ........................................................................................ 25
Figure 6-8. ESD Layout Recommendations ........................................................................... 25
Figure 6-9. PCIe Root Port Connections Example ................................................................. 27
Figure 6-10. PCIe Endpoint Connections Example .................................................................. 28
Figure 6-11. Insertion Loss S-Parameter Plot (SDD21) .......................................................... 30
Figure 6-12. Insertion Loss S-Parameter Plot (SDD11) .......................................................... 31
Figure 6-13. AC Cap Voiding ..................................................................................................... 31
Figure 6-14. Connector Voiding ................................................................................................ 31
Figure 6-15. Example Zig-Zag Routing .................................................................................... 33
Figure 7-1. Ethernet Connections .......................................................................................... 36
Figure 7-2. Gigabit Ethernet Magnetics and RJ45 Connections ........................................... 36
Figure 8-1. DP and eDP Connection Example ....................................................................... 40
Figure 8-2. eDP and DP Differential Main Link Topology ..................................................... 41
Figure 8-3. S-Parameter (up to HBR2) ................................................................................... 43
Figure 8-4. S-Parameter (up to HBR3) ................................................................................... 44
Figure 8-5. Via Topology #1 .................................................................................................... 44
Figure 8-6. Via Topology #2 .................................................................................................... 44
Figure 8-7. HDMI Connection Example .................................................................................. 46
Figure 8-8. HDMI Clk and Data Topology ............................................................................... 47
Figure 8-9. IL/FEXT Plot .......................................................................................................... 50
Figure 8-10. TDR Plot ................................................................................................................ 50
Figure 8-11. HDMI Via Topology ............................................................................................... 51