Rievtech PR-6DC-DA-R - AND with Edge Evaluation

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Input1
Input2
Input 3
Input 4
Output
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
1
0
0
1
1
0
0
0
1
1
1
0
1
0
0
0
0
1
0
0
1
0
1
0
1
0
0
1
0
1
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
0
0
1
1
1
1
1
5.3.2 AND with edge evaluation
Fashion: Classic: (Symbol in xLogic)
The output of an AND with edge evaluation is only 1 if all inputs are 1 and at least one input was 0
during the last cycle.
The output is set to 1 for the duration of one cycle and must be reset to 0 for the duration of the next cycle
before it can be set to 1 again.
A block input that is not used (x) is assigned: x = 1.
Timing diagram of an AND with edge evaluation