3.2
SEL-551 Relay Instruction Manual Date Code 20110408
Relay Elements and Logic
Relay Word Bits and SEL
OGIC Control Equations
In addition to Relay Word bits, numerals:
1 (logical 1) or 0 (logical 0)
can be entered in a SEL
OGIC control equations setting. If a SELOGIC control
equation setting is set equal to 1, it is always “asserted/on/enabled.” If a
SEL
OGIC control equation setting is set equal to 0, it is always “deasserted/off/
disabled.” Under the SHO Command (Showset), note that a number of the
factory SEL
OGIC control equation settings are set equal to 1 or 0.
Limitations
Any single SELOGIC control equation setting is limited to nine Relay Word
bits that can be combined together with the SEL
OGIC control equation
operators listed in Table 3.1. To get around this limitation, a SEL
OGIC Variable
(SEL
OGIC control equation settings SV1–SV14) can be used as an
intermediate setting step.
For example, presume that the trip equation (SEL
OGIC control equation setting
TR) needs more than nine Relay Word bits in its equation setting. Part of the
desired equation is put into the SEL
OGIC control equation setting SV1. The
resultant SEL
OGIC Variable output (Relay Word bit SV1) is then set in
SEL
OGIC control equation setting TR.
Note in Table 3.2 that the SEL
OGIC Variables (SELOGIC control equation
settings SV1–SV14) are processed after the trip equation (SEL
OGIC control
equations setting TR). Thus, any tripping via Relay Word bit SV1 is delayed
one processing interval (1/8-cycle). For most applications, this is probably of
no consequence.
For all the SEL
OGIC control equations settings in total, the SEL-551 relay has
limits of 235 Relay Word bits that can be combined together with the
SEL
OGIC control equation operators listed in Table 3.1.
Up to 16 total rising-edge and falling-edge detects can be used in SEL
OGIC
control equations settings for the SEL-551 relay.
Processing Order and
Processing Interval
The relay elements and logic (and corresponding SELOGIC control equation
settings and resultant Relay Word bits) are processed in the order shown in
Table 3.2 (top to bottom). They are processed every eighth-cycle (1/8-cycle),
and the Relay Word bit states (logical 1 or logical 0) are updated with each
eighth cycle pass. Thus, the relay processing interval is 1/8-cycle. Once a
Relay Word bit is updated during an eighth-cycle pass, it retains the state
(logical 1 or logical 0) until it is updated again on the next eighth-cycle pass.
The Display Points (DP1–DP8) are described in Section 6: Front-Panel
Interface. The Event Report Triggers (ER1 and ER2) are described in
Section 7: Standard Event Reports and SER. The other items in Table 3.2 are
described in the rest of this section, in the order given in Table 3.2. The
exception to this order is Demand Ammetering on page 3.41.
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