Chapter 2 Basic Unit Specification
4. High speed input
2-29
4.5.2 Action of 2 phase input signal
z 2 phase encoder can produce A phase and B phase with 90° phase difference to A phase. Such
high speed counter can automatically up count or down count.
z The following indicates operation of 2 phase counter.
A phase
B phase
+1 +1 -1 -1
→Time
Forward: up counting Reverser: down counting
A phase
B phase
→Time
4.6 Output counting result
The output should be enabled immediately as long as the present value reaches the set value of
high speed counter, so the special application instructions should be used.
A. <<Comparison set/reset instruction for high speed counter>>
z When reaching the comparison value, the
interruption will be on (Y000 ON).
z Please select transistor output type. As for
relay output type, the PLC has a mechanical
delay about 10ms.
B. <<Zone comparison instruction for high speed counter>>
z Zone comparison instruction of high-speed
K10＞C241 present value →Y000 ON
K10＜C241 present value＜K20 →Y001 ON
C241 present value＞K20 →Y002 ON
Regarding to general application instruction F10 (CMP) and FNC11 (ZCP), there will be a delay
because of PLC scan time. In order to avoid that delay in high speed counting, the above
instructions F53, F54 and F55 have nothing to do with scan time and the output will operate
immediately.
4.7 Restrictions for fastest responding frequency
Regarding to hardware, the input X000~X005 has the competence to accept 100 kHz signal.
However, with respect to software, please take the following items into consideration:
A. When C235
～
C238,C241,C242,C244,C245 are set as up-counting counter, its max
frequency could be 100KHz.
B. When C235
～
C238,C241,C242,C244,C245 are set as up/down counting counters or as
down-counting ones, its max frequency could be 5KHz.
C. The C239
～
C240,C243,C246~C249 counters could accept the max frequency, 5KHz
D. The C251
～
C254 counters could accept the max frequency 100KHz.
E. When the system is preoccupied by a lot of other functions (such as frequent
communication/ longer program/longer scan time/ many interruptions/ pulse output/
compare instruction for high speed counter), it is suggest that the max average frequency
of high speed counter should be decreased properly.
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