VIPA CPU 21 Series - Page 217

Manual VIPA CPU 21x Chapter 7 Deployment of the CPU 21xDP
HB103E - Rev. 05/45 7-25
Multi master system
More than one master and multiple slaves connected to one bus:
3
Input/output periphery
CPU 21x DP
5
Input/output periphery
CPU 21x DP
CPU IM 208
5
CPU IM 208
1,3
IM 253
1
Input/output periphery
IM 253
2
Input/output periphery
CPU IM 208
2,4
IM 253
4
Input/output periphery
Input/output periphery