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VIPA CPU 21 Series User Manual
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Manual VIPA CPU 21x
Chapter 7 Deployment of the CPU 21xDP
HB103E - Rev. 05/45
7-25
Multi mast
er sy
stem
More than one master and mult
iple slaves connected to one bus:
3
Input/output
peripher
y
CPU 21x DP
5
Input/output p
eripher
y
CPU 21x DP
CPU
IM 2
08
5
CPU
IM 208
1,3
IM 253
1
Input/outpu
t periphe
ry
IM 253
2
Input/outpu
t periphe
ry
CPU
IM 208
2,4
IM 253
4
Input/outpu
t periphe
ry
Input/outpu
t periph
ery
216
218
Table of Contents
Default Chapter
4
About this Manual
4
Table of Contents
7
User Considerations
11
Safety Information
12
Chapter 1 Principles
13
Chapter 1 Principles
14
Safety Information for Users
14
Hints for the Deployment of the MPI Interface
15
Hints for the Green Cable from VIPA
16
Overview System 200V
17
Function Security of the VIPA Cpus
18
General Description of the System 200V
19
Overview CPU 21X
20
Hints for Project Engineering
21
Application Fields
25
Features
26
Operating Modes of a CPU
27
CPU 21X Operands
28
CPU 21X Programs
28
Chapter 2 Hardware Description
31
Chapter 2 Hardware Description
32
System Overview
32
Structure
41
Components
43
Block Diagram
52
Technical Data
53
Chapter 3 Deployment CPU 21X
59
Assembly
60
Chapter 3 Deployment CPU 21X
61
Start-Up Behavior
61
Address Allocation
62
Project Engineering
64
Configuration of the CPU Parameters
67
Project Transfer
69
Operating Modes
72
Overall Reset
73
Firmware Update
75
Using Test Functions for the Control and Monitoring of Variables
78
Chapter 4 Deployment of the CPU 21X-2BT10 with TCP/IP
81
Chapter 4 Deployment of the CPU 21X-2BT10 with TCP/IP
82
Industrial Ethernet in Automation
82
ISO/OSI Reference Model
83
Principles
86
Protocols
87
IP Address and Subnet
90
Network Planning
92
Communication Possibilities of the CP
95
Function Overview
98
Fast Introduction
99
Hardware Configuration
103
Configure Connections
106
SEND/RECEIVE with PLC Program
112
Project Transfer
117
NCM Diagnostic - Help for Error Diagnostic
119
Coupling to Other Systems
122
Example Communication Cpu21X-2BT10
125
Chapter 5 Deployment CPU 21X-2BT02 with H1 / TCP/IP
131
Chapter 5 Deployment CPU 21X-2BT02 with H1 / TCP/IP
132
Principles
132
Network Planning
137
Ethernet and IP Addresses
139
Project Engineering of the CPU 21X-2BT02
141
Configuration Example CPU 21X-2BT02
154
Start-Up Behavior
165
System Properties of the CPU 21X-2BT02
166
Communication to Other Systems
168
Test Program for TCP/IP Connections
171
Chapter 6 Deployment of the CPU 21Xdpm
179
Chapter 6 Deployment of the CPU 21Xdpm
180
Principles
180
Project Engineering CPU with Integrated Profibus-DP Master
183
Project Transfer
187
DP Master Operating Modes
190
Commissioning and Start-Up Behavior
191
Chapter 7 Deployment of the CPU 21Xdp
193
Chapter 7 Deployment of the CPU 21Xdp
194
Principles
194
CPU 21Xdp Configuration
199
DP Slave Parameters
204
Diagnostic Functions
207
Internal Status Messages to CPU
210
Profibus Installation Guidelines
212
Commissioning
218
Example
220
Chapter 8 Deployment CPU 21Xcan
225
Chapter 8 Deployment CPU 21Xcan
226
Principles CAN-Bus
226
Project Engineering of the CPU 21Xcan
228
Modes
237
Process Image of the CPU 21Xcan
238
Canopen - Messages
240
Object Directory
245
Chapter 9 Deployment CPU 21Xser-1
259
Chapter 9 Deployment CPU 21Xser-1
260
Fast Introduction
260
Protocols and Procedures
261
Deployment of the Serial Interface
265
Principles of Data Transfer
266
Parameterization
268
Communication
272
Modbus Slave Function Codes
278
Modbus - Example Communication
282
Chapter 10 Deployment CPU 21Xser-2
287
Principles
288
Chapter 10 Deployment CPU 21Xser-2
289
Protocols and Procedures
289
RS232C Interface
293
Communication
294
Initialize Interfaces
295
Interface Parameters
297
Interface Communication
300
Integrated Obs Sfbs Sfcs
303
Integrated Obs and Sfbs
305
Integrated Standard Sfcs
306
VIPA Specific Sfcs
308
Chapter 11 Integrated Obs Sfbs Sfcs
309
Include VIPA Library
309
Sfc 216 Ser_Cfg
310
Sfc 217 Ser_Snd
312
Sfc 218 Ser_Rcv
313
Sfc 219 Can_Tlgr
314
Sfc 220 Mmc_Cr_F
317
Sfc 221 Mmc_Rd_F
319
Sfc 222 Mmc_Wr_F
320
Sfc 223 Pwm
321
Sfc 224 Hsc
323
Sfc 225 Hf_Pwm
325
Sfc 227 - Td_Prm
327
Sfc 228 - Rw_Kachel
329
Page Frame Communication - Parameter
331
Page Frame Communication - Parameter Transfer
334
Page Frame Communication - Source Res. Destination Definition
335
Page Frame Communication - Indicator Word ANZW
338
Page Frame Communication - Parameterization Error PAFE
345
Sfc 230 - Send
346
Sfc 231 - Receive
347
Sfc 232 - Fetch
348
Sfc 233 - Control
349
Sfc 234 - Reset
350
Sfc 235 - Synchron
351
Sfc 236 - Send_All
352
Sfc 237 - Receive_All
353
Sfc 238 - Ctrl1
354
Chapter 12 Instruction List
355
Alphabetical Instruction List
356
Chapter 12 Instruction List
356
Abbreviations
359
Registers
361
Addressing Examples
362
Math Instructions
365
Block Instructions
367
Edge-Triggered Instructions
368
Program Display and Null Instruction Instructions
368
Load Instructions
369
Shift Instructions
372
Setting/Resetting Bit Addresses
373
Jump Instructions
374
Transfer Instructions
376
Data Type Conversion Instructions
379
Comparison Instructions
380
Combination Instructions (Bit)
381
Combination Instructions (Word)
387
Timer Instructions
387
Counter Instructions
388
VIPA Specific Diagnostic Entries
389
Index
391
Appendix
391
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VIPA CPU 21 Series Specifications
General
Brand
VIPA
Model
CPU 21 Series
Category
Control Unit
Language
English
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