Xerox 560 Reference Manual

Bit
Position
Designation.
Function
8
MS Master/slave mode control
9
MM Memory map mode control
10
DM
Decimal arithmetic trap
mask
11
AM Fixed-point arithmetic
overflow trap mask
15-31
IA Instruction address
32-35
WK
Write key
37 CI
Counter interrupt group
inhibit
38
II
I/O interrupt group inhibit
39
EI External interrupt inhibit
56-59 RP
Reg i ster po inter
60
RA Register altered
61 MA
Mode altered
The detailed functions of the various portions of the program
status words are described in Chapter 2, "Program Status
Words".
LPSD
LOAD PROGRAM STATUS WORDS
(Doubleword index alignment, privileged)
LOAD PROGRAM STATUS WORDS replaces bits o through 39,
60 and 61 of the current program status words with bits 0
through 39, 60 and 61 of the effective doubleword.
Control bits used in the LPSD instruction are:
Bit
Position
Designation
Control Function
8
LP
Load pointer control
10
Cl
Clearing of interrupt level
11
AD Armed/disarmed state
The following conditional operations are performed:
1. If bit position 8 (LP) of LPSD conta ins a 1, bits 56
through 59 (register pointer) of the current program
status words are replaced by bits 56 through 59 of the
effedive doublewOid; if bit 8 of LPSD is u 0, tht=: cu,--
rent register pointer value remains unchanged.
2. If bit position 10(CL}of LPSD contains a 1, the highest
priority interrupt level currently in the active state is
cleared (i. e., reset to either the armed state or the dis-
armed state); the interrupt level. is armed if bit 11 (AD)
110 Control Instructions
of lPSD is a 1, or is disarmed if bit 11 of LPSD is a O.
If bit 10 of lPSD is a 0, no interrupt level is affected
in any way, regardless of whether b-it 11 of LPSD is 1
or O. If bit 10 of the lPSD is a 0 and bit 11 of lPSD
is 1, the PDF flag is cleared. (Interrupt levels are de-
scribed in detai I in Chapter 2, "Interrupt System". )
Bit position
10 (CL) 11 (AD) Function
o Clear and disarm interrupt level.
Clear and arm interrupt level.
o
Clear PDF flag.
o
o
No control action.
3. The PDF flag is normally reset by the last instruction
of a trap routine, which is an LPSD instruction having
bit 10 equal to 0 and bit 11 equal to 1.
These portions
of the effective doubleword that correspond
to undefined fields in the program status words are ignored.
Affected: (PSWs), interrupt system if (1)10 = 1
ED
O
_
3
- CC; ED
5
_
7
-
FS,FX,FN;
ED -MS' ED - MM·
8 '9 '
ED
15
_
31
- IA; ED
32
_
35
- WK;
ED
37
_
39
- CI, II, EI; if (1)8 = 1, ED
56
_
59
- RP
ED60 - RA; ED61 - MA
u: In = 1 ~ ... ,J In
"\"10 · .... ·1\··\·'11
= 1
. , C!CCi and aim iiitcirupt
If (1)10 = 1 and (1)11 = 0, clear and disarm interrupt
XPSD
EXCHANGE PROGRAM STATUS WORDS
(Doubleword index alignment, privileged)
EXCHANGE PROGRAM STATUS WORDS stores the cur-
rently active PSWs in the doubleword location addressed by
the effective address of the XPSD instruction. The follow-
ing doubleword is then accessed from memory and loaded
into the active PSWs registers.

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